Advanced FPGA Design tackles the most sophisticated aspects of the ISE 11.3 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 11.3 tools and the Virtex-6 and Spartan-6 FPGAs.

This course focuses on providing, ASIC / FPGA designers with the Xilinx tool-set flow. Current designers will get familiar with the various Xilinx tools, (ISE, XST, MAP, Place and Route, Trace ) and design techniques. HDL inference of FPGA resources and coding examples are provided. The course highlights the Virtex™-IV family though most concepts can also be applied to Virtex-based designs. HDL inference of FPGA resources and coding examples are provided.

Learn how to employ RocketIO GTP serial transceivers in your Virtex-5 LXT FPGA design, utilize the features of the RocketIO transceiver blocks, CRC, 8B/10B encoding, channel bonding, clock correction, and comma detection. Additional highlighted topics include use of the Architecture Wizard and synthesis and implementation considerations. This course balances lecture modules and practical hands-on labs.

This intermediate-level course provides embedded systems developers with experience in creating an embedded open-source Linux operating system on a Xilinx development board. The course offers students hands-on experience from building the environment to booting the system using a basic, single-processor System on Chip (SoC) design with Linux 2.6 from the Xilinx kernel tree.

This course introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging/profiling options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow.

Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families. Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.