| Course Name | Price NIS before VAT | June | Brief Description |
| PCI Express designing Flow | 3780 / 9 | 01 | Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system with supporting logic and example designs. Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the Virtex™-5 FPGA PCIe Endpoint Block Plus and the Spartan™-3 PCIe integrated Endpoint PIPE block. |
| SystemVerilog | 5040 / 12 | 02-05 | This comprehensive 3-day hands-on intensive course provides complete and integrated training program. It is structured as a comparison between traditional Verilog 1995 and newer Verilog standards 1364-2001 and 1800-2005 SystemVerilog. The goal of this course is to fulfill the needs and requirements for engineers, who want to exploit wide breadth of SystemVerilog features for both design and verification. |
| Designing with the Virtex-5 LX FPGA | 1260 / 3 | 05 | Effectively utilize Virtex-5 FPGA architectural resources. Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing. Topics covered include a Virtex-5 FPGA overview, new LUT, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. |
| Advanced FPGA Implementation | 3780 / 9 | 10-12 | Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE tool suite and Xilinx hardware. Eight labs provide hands-on experience in this two-day course and cover Synplicity’s Synplify, Mentor’s Precision, and the Xilinx XST tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended, as is at least sixMonths’ design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE software tools and the Virtex-II and Virtex-4 FPGAs. |
| Symbian OS: Essentials | 5040 | 10-12 | Hands on” course aimed at developers new to C++ programming for the Symbian OS. It covers the following areas: development tools, application development, E32 User Library, resource management, descriptors, arrays, file server, stream store, active objects and client server architecture. The Essentials course explores the essential programming techniques required by all Symbian OS developers and acts as a foundation course to the more specialised Application UI and Application Engines courses. Details of these courses are available on request. |
| Designing with Multi-Gigabit Serial I/O | 3780 / 9 | 15-17 | Learn how to employ RocketIO GTP serial transceivers in your Virtex-5 LXT FPGA design, utilize the features of the RocketIO transceiver blocks, CRC, 8B/10B encoding, channel bonding, clock correction, and comma detection. Additional highlighted topics include use of the Architecture Wizard and synthesis and implementation considerations. This course balances lecture modules and practical hands-on labs. |
| Designing with the Virtex-5 for the Virtex Users | 5880 / 14 | 17-19 | Virtex-5 allows, among other things, considerably more effective implementations with the 6-input LUT, better block-RAM and FIFO implementations, high speed memory interfaces, and extended DSP applications. The 3-day workshop teaches experienced VirtexIIPro/Virtex-4 users how to use the Virtex-5 design resources. It focuses on describing the new or modified architectural elements and their optimum implementation with VHDL. It also covers software support through CoreGen or Architecture Wizards. The theoretical content is rounded off with practical exercises on the PC. |
| FPGA and ISE Design | 2520 / 6 | 18-19 | Use the ISE™ software tools to design and understand Xilinx FPGA architecture, Xilinx design flow, ISE features, Architecture Wizard, Pin and Area Constraint Editor (PACE), design planning, implementation options, and global timing constraints |
| Designing with Xilinx Ethernet MAC Controller | 2520 / 6 | 22-23 | Learn Various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements. |
| Signal Integrity and Board Design | 5880 / 14 | 22-24 | The 3-day workshop “Signal Integrity and Board Design” is aimed at developers who want to implement high-speed interfaces between a XILINX FPGA and external semiconductor components and who want to design complex high-speed FPGA at board level. This Workshop is designed for developers who not only design FPGAs but also systems and the layout. |
| DSP Design Data Flow | 3780 / 9 | 24-25 | The DSP Design Flow course provides the advanced tools and expertise you need to develop advanced, low-cost DSP designs. This course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, HDL co-simulation, and hardware-in-the-loop verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities. |
| Advanced Verilog for Designers | 2520 / 6 | 25-26 | This course focuses on advanced simulation techniques that among other things leverage the enhanced Verilog 2001 File IO capabilities. The course covers writing user-defined subprograms (tasks and functions) as part of creating a robust verification strategy. The course also demonstrates important proprietary tool features and concepts, such as Code Coverage from MTI’s ModelSim product, and Xilinx’s own ISIM tool. FPGA device level optimization is also discussed, from the standpoint of Verilog RTL coding, including using and simulating Xilinx CoreGen modules. In addition, back-annotated timing simulation techniques are demonstrated.This course will enhance testing and verification skills for existing Verilog designers while improving qualityof- results for FPGA based applications. |
| Chipscope | 1260 / 3 | 29 | As FPGA designs become increasingly more complex, designers are searching to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for debug and verification. This one-day course will show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges. |