Hardware Training

This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow.
For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.

Level

FPGA 1
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Learn to increase design performance and achieve repeatable results, plan an I/O pin layout, and implement by using the PlanAhead software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool, synthesis and project tips, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope Pro tool, and design preservation with partitions.

Level:

Intermediate

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Attending the Designing for Performance class will help you create more efficient FPGA designs. This course will enable you to optimize your design for usage in a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Level:

FPGA3

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This course tackles the most sophisticated aspects of the Vivado® Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.

Level:

FPGA 4
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Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.

Level:

FPGA 3

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Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express® technology, analog to digital converters and gigabit transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.

Level:

FPGA3 

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Learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the UltraScale FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.

Level:

Connectivity 3

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This course focuses on providing ASIC/ FPGA experienced designers with the Xilinx tool-set flow. Current designers will get familiar with the various Xilinx tools, (ISE, XST, MAP, Place and Route, Trace…) and design techniques. HDL inference of FPGA resources and coding examples are provided. The course highlights the Virtex-IV family though most concepts can also be applied to Virtex-based designs. HDL inference of FPGA resources and coding examples are provided.

Level:

Intermediate to Advanced

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Attending the Tips & Tricks for FPGA Design class will enrich your knowledge in several aspects of the FPGA design world. This 1 day seminar will enable you to get familiar with new aspects and problems you may encounter during your project flow. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, lower the design risk and development costs.

Level:

Intermediate

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FPGA Introduction assuming VHDL is a known language.
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This course will update experienced ISE software users to utilize the Vivado Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado timing engine. Finally, you will learn about the scripting environment of the Vivado Design Suite and how to use the project-based scripting flow.
You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.

Level:

FPGA 2
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This course demonstrates how to use the ISE®, PlanAhead™, and Embedded Development Kit (EDK) software tools to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow.
This course covers both the tool flow and mechanics of successfully creating a PR design. It also describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications.

Level:

FPGA 4

Skills Gained:

After completing this training, you will be able to:

• Build and assemble a Partially Reconfigurable system
• Define PR regions and reconfigurable modules with the PlanAhead software
• Generate the appropriate bitstreams targeting Platform Flash and System ACE™ interface tool files to support on-board partial bitstream storage
• Use the ChipScope™ Pro tool to monitor/debug the ICAP component
• Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
• Implement a PR system using the following techniques:
  • Direct JTAG connection
  • HDL state machines
  • Timing constraints and analysis
  • Microprocessor-based designs

Recommended Courses:

Embedded Systems Development course
Essential Design with the PlanAhead Analysis and Design Tool course
Advanced Design with the PlanAhead Analysis and Design Tool

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This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, re-usable tasks and functions, and packages, are      all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.

Level:

FPGA1
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Learn how to use basic Tcl syntax and language structures to build scripts suitable for use with Xilinx FPGA design tools. Learn about the effective use of variables, data types, and Tcl constructs to build effective conditional statements and loop controls. You will also have the opportunity to use Tcl language constructs with several labs designed to provide you scripting experience within the Vivado™ Design Suite.

Level: FPGA 1
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This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs.

Level:

FPGA 1
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VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
Expert VHDL is an intensive 6-days advanced application class. It teaches engineers how to increase productivity by enhancing their VHDL coding and application skills. Presented in two distinct course modules, Expert VHDL focuses on language and synthesis issues, design maintainability and re-use, test benches and the latest techniques for verification - including an introduction to OVL and modern assertion-based approaches to verification.

• Expert VHDL- Advanced Digital Design (3 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL, and to improve their VHDL coding style with design maintainability and re-use in mind. Design for Verification is also covered with an introduction to modern assertion-based techniques.
• Expert VHDL Verification (3 days) is for design engineers and verification engineers involved in VHDL test bench development or behavioral modeling for the purpose of functional verification.

The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.
Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.  

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This comprehensive 4-days hands-on intensive course provides complete and integrated training program. It provides the participants with a deep knowledge of 1800-2005 SystemVerilog. The goal of this course is to fulfill the needs and requirements of engineers wanting to exploit the breadth of SystemVerilog features for both design and verification.

Level:

Intermediate to Advanced

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VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice. This training builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.

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Course description with information on the course – marketing oriented.
Open Verification Methodology (OVM) is a non-proprietary functional verification methodology based on SystemVerilog. The source code and documentation are freely available under an open-source Apache license. OVM offers a complete framework for the creation of sophisticated functional verification environments in SystemVerilog, and encourages the development and deployment of re-usable verification components.
It has comprehensive support for constrained random stimulus generation, including structured sequence generation, and for transaction-level modelling. OVM testbenches also support functional coverage collection and assertions. OVM exploits the object-oriented programming (or "class-based") features of SystemVerilog. The open structure, extensive automation, and standard transaction-level interfaces of OVM make it suitable for building functional verification environments ranging from simple block-level tests to the most complex coverage-driven testbenches.
Delegates for this course must start with a detailed knowledge of building class-based verification environments using SystemVerilog. The course leads delegates through to full verification project readiness by focussing on the in-depth practical application of OVM using commercial verification tools such as Mentor Graphics Questa™Sim and Synopsys® VCS®.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. During the hands-on workshops, delegates will build a complete OVM verification environment for a small example system.

Level: Standard Level OVM Training
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The Universal Verification Methodology (UVM) is a standard functional verification methodology for SystemVerilog, controlled by Accellera, and endorsed and supported by all major SystemVerilog simulator vendors. The source code and documentation are freely available under an open-source Apache license. UVM offers a complete framework for the creation of sophisticated functional verification environments in SystemVerilog, and encourages the development and deployment of re-usable verification components.
UVM has comprehensive support for constrained random stimulus generation, including structured sequence generation, and for transaction-level modeling. UVM testbenches also support functional coverage collection and assertions. UVM exploits the object-oriented programming (or "class-based") features of SystemVerilog. The open structure, extensive automation, and standard transaction-level interfaces of UVM make it suitable for building functional verification environments ranging from simple block-level tests to the most complex coverage-driven testbenches.
Delegates for this course must start with a detailed knowledge of building class-based verification environments using SystemVerilog. The course leads delegates through to full verification project readiness by focusing on the in-depth practical application of UVM using commercial verification tools such as Cadence Incisive® Enterprise Simulator, Mentor Graphics Questa™Sim, and Synopsys® VCS®.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. During the hands-on workshops, delegates will build a complete UVM verification environment for a small example system.
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SystemVerilog (IEEE 1800™) is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture.
SystemVerilog for Verification Specialists provides a 4 day training program to fulfil the requirements of verification engineers or those wishing to evaluate SystemVerilog's applicability for complex verification application. It is structured to enable engineers to develop their skills to utilise the full breadth of SystemVerilog features for verification. This includes how to exploit the potential of class-based verification and object oriented techniques using SystemVerilog, as well as application for standard test bench development and module-based verification.
The course assumes Verilog knowledge but no prior SystemVerilog knowledge. VHDL users preparing to use SystemVerilog should consider preparatory training with the 2 day Fast Track Verilog for VHDL Users.
The course includes an introduction to UVM (and OVM) but full scope project readiness in UVM requires follow-on training with the 3 day UVM Adopter Class.
Design engineers (FPGA or ASIC) who intend to use SystemVerilog for RTL design and basic test bench development should attend the companion training course SystemVerilog for FPGA/ASIC Design.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.
Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology.

Level: Standard Level
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VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
This trainingprepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.
Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. 

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This course will help software engineers fully utilize the components available in the Zynq® All Programmable System on a Chip (SoC) processing system (PS). This course covers advanced Zynq All Programmable SoC topics for the software engineer, including advanced boot methodology, the NEON co-processor, programming PS system-level function control registers, the general interrupt controller, the DMA, Ethernet, and USB controllers, and the various low-speed peripherals included in the Zynq All Programmable SoC processing system.

Level:

Embedded Software 4
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This course is broken into a day of C language review, including variable naming, usage, and modifiers as well as an introduction to the Software Development Kit (SDK) environment, an explanation of the use of the preprocessors, program control, and proper use of functions. The second day consists of common issues and techniques employed by embedded programmers in the Xilinx SDK environment. This comprehensive course equally balances lecture modules with practical hands-on lab work.

Level: Embedded 1
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This one-day course is structured to help designers new to the SDSoC™ development environment to quickly create accelerated systems. The focus is on utilizing the tools to accelerate an existing design at the system architecture level, not on the optimization of the accelerator microarchitectures.
Several optional modules are provided to quickly provide students with the necessary background on both hardware and software. The first half of this class is Level 1 while the afternoon's topics are at Level 2. .
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This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado Design Suite. The features and capabilities of both the Zynq All Programmable System on a Chip (SoC), Zynq UltraScale+ MPSoC, and the MicroBlaze™ soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.
The Xilinx Zynq families enable a new level of system design capabilities over previous embedded technologies, which is highlighted throughout the course.

Level:

Embedded Hardware 3

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Learn what makes microprocessors tick! This class offers insights into all major aspects of microprocessors, from registers through coprocessors and everything in between. Differences between RISC and CISC architectures are explored as well as the concept of interrupts. A generic microprocessor is programmed and run in simulation to reinforce the principles learned in the lecture modules. The student will leave the class well prepared for the Xilinx Zynq training curriculum.

Level:

Embedded 1

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Custom processor accelerators are quickly becoming standard practice for reaching system performance goals. This one-day introduction to the accelerator development flow focuses on how to measure system performance, determine what software functionality should be moved to hardware, how to assemble a custom accelerator using the Vivado® HLS tool, add the custom accelerator to a Zynq® All Programmable SoC design, and finally measure accelerated performance.
Emphasis is placed on the Zynq AP SoC's architectural features that make coupling an accelerator to the multi-processor core a possibility as well as the many techniques for implementing accelerated systems. Discussion of typical tradeoffs that a system architect will likely make is also included. The specifics of the accelerator itself is secondary as the focus is on how to integrate an accelerator rather than accelerator design techniques.

Level:

Embedded 2
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The half-day and one-day seminars will focus on some key challenges commonly encountered in developing embedded systems and how using the Zynq®-7000 All Programmable SoC (AP SoC) devices allays many of these situations.
The seminars are equally designed for networking, vision, and generic designers to help them identify their challenges and discover why Zynq-7000 devices are the right fit for their applications. The seminars and demos will also help students choose the appropriate path in the Zynq Smarter Solutions Workshop
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This one-day workshop introduces you to software design and development for the Zynq® All Programmable System on a Chip (SoC) using the Xilinx Software Development Kit (SDK). The focus is on the basic features and capabilities of the Zynq All Programmable SoC as well as the tools and techniques required for the software phase of the design cycle.
The hands-on labs provide students experience with the design and implementation of the software application and the board support package (BSP) for resource access and management of the Xilinx Standalone library. Labs also include debugging a remote server Linux application, profiling for performance, and interrupts.
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This two-day course is structured to provide software developers with a catalog of OS implementation options, including hypervisors, various Linux implementations, booting and configuring a system, and power management for the Zynq® UltraScale+™ MPSoC family.

Level:

Embedded Software 3
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This course takes an in depth look at the considerations you will need to take into account when designing a system containing a Cortex-A9 core

It is aimed at:
Software engineers who not only want to obtain details of how to write software to run on the Cortex-A9, but also wish to obtain an understanding of hardware design issues
Hardware engineers who need to understand how to design Cortex-A9 based systems, but also wish to obtain an understanding of the issues of writing software to run on that system.

Level: Intermediate


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C-based coding is increasingly used for the modeling and high-level synthesis of hardware components. This course provides hardware engineers with sufficient knowledge of C-programming techniques for Vivado™ HLS to take advantage of Xilinx FPGAs. Learn high-level synthesis best practices, methodology, and subtleties of C-based coding for hardware modeling, synthesis, and verification.

Level: DSP 3
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This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.

Level:

DSP 3
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The workshop introduces you to fundamental DSP concepts, algorithms, and techniques for implementation in Xilinx FPGAs. Design examples and labs are drawn from several common applications spaces, including wireless communications, video, and imaging.
Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses.
The material is also complementary to the Avnet SpeedWay Design Workshop on FPGA-Based System Design with High-Speed Data Converters.

Level: DSP 3
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Many applications in today's technological world require fast DSP processing. Anything from physical layer processing in communication infrastructure to extraordinary image and sound processing in medical equipment. DSP is a unique area in VLSI design. There are many ways to implement the same DSP algorithm, though the efficient implementation may not be so obvious and would usually require particular expertise.The course introduces important basic concepts in DSP designing, surveys a variety of structures and advanced DSP implementations in VLSI.
The course is largely based on examples and relevant hands-on analytical exercises.
 

Level:

Intermediate

 

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Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.

Level:

Connectivity 3
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Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements. Become familiar with Ethernet IP core design architectures, core IP port naming conventions, and signal waveforms.
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In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.

Level:

Connectivity 3

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FPGA Introduction assuming VHDL is a known language.
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This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs.
Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.
The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR, and QDRII+. Labs are available for DDR3 on the Kintex™-7 FPGA KC705 board.

Level:

Connectivity 3

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Course Description
Are you interested in learning how to effectively utilize 7 series high-speed interface resources? This course supports both experienced and less experienced FPGA designers who have in minimum general digital hardware knowledge and basic information on 7 series FPGAs. Furthermore, first work with the new Xilinx VIVADO Design Suite is helpful.  This course focuses on understanding as well as how to properly design for the high-speed interface solutions found in the new device families: transceiver in general, PCI Express and memory interfacing complemented with board design issues. Topics covered include interface overviews, design usage, simulation, implementation and examples on real hardware.
This course also includes a detailed discussion about proper PCB design techniques that enables designers to avoid common mistakes and get the most out of their FPGA interfaces.
A combination of modules and labs allow for practical hands-on application of the principles taught.
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PCI Express is the open standards- based successor to PCI and its variants for server- and client-system I/O interconnects. Unlike PCI and PCI-X, which are based on 32- and 64-bit parallel buses, PCI Express uses high-speed serial link technology similar to that found in Gigabit Ethernet, Serial ATA (SATA), and Serial-Attached SCSI (SAS). PCI Express reflects an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses.

In this training we will discuss and cover the following:

• Packet switching benefits compared to shared busses are highlighted
• The course explains the various traffic types that PCI Express supports
• The use of virtual channels to match Quality of Service requirements is explained
• The course describes the discovery sequence required to initialize the switches
• The course details the various stages of the physical layer : 8b10b and 128/130b coding, scrambling, elastic buffer, clock recovery and link training sequence
• The course highlight the differences between the 3 generations of PCI Express 

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Learn when and how to apply power & signal integrity techniques to high-speed interfaces between components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.

Level:

Connectivity 3 

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Attending the Tips & Tricks for Board Design class will enrich your knowledge in several features of current board design. This 1 day seminar will familiarize you with new aspects and problems you may encounter during project development. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to design faster, shorten development time, lower development costs and lower design risk.

Level:

Intermediate

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Over the years the use of communication networks has not only increased but also changed dramatically. Carriers today are aiming for a converged network that will supply data, audio and video communication on the same network infrastructure, providing a wide variety of new applications alongside the classical telephony, internet surfing, and TV broadcasting. To meet that goal the routers and switches in these networks and their underlying HW engines must improve. The HW engines are required to do diverse tasks from parsing and editing the packets, through forwarding them to scheduling them. Applying the right mechanisms for these diverse, demanding tasks requires an understanding in both networking and chip design. This course will discuss the context between the two fields with samples of Xilinx' implementations.

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Attending this course will give you principles in using and designing Digital Image Processing algorithms used in the academy and industry today. Some ®MATLAB tools will be demonstrated as part of the training.

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This course presents the essentials of Electronics engineering and Hardware Design for software engineers. The course is a complete tour of the fundamentals of electrical engineering. It will enable the software engineer that works with an electronics engineer’s better communicate and understand the electrical engineering when working on a common project. The course presents examples of all the learning material.

Level:

Fundamental
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• תלמד/י עקרונות ומתודולוגיות פיתוח כרטיסים מודפסים
• תלמד/י את העקרונות של High Speed Signal Integrity תוך שימוש בכלים למטרות סימולציה
• כל סטודנט יבצע פרויקט של תכנון מעגל מודפס המכיל את כל השלבים:
  • ארכיטקטורה, תכנון, שרטוט, עריכה ובדיקה במעבדה 
  • העבודה המעשית והפרויקט יתבצעו תוך שימוש בכלי התכנון המובילים בארץ (Cadence, Mentor)
• תבין/י לעומק את עקרונות הייצור של מעגל מודפס כולל תכנון להעברה ליצור, בניית השכבות ובדיקות המוצר לאחר היצור
• תקבל/י הדרכה מעורך מעגלים על עריכת המעגלים של הכרטיס
• יערך סיור אצל יצרני מעגלים על מנת להבין ולאפיין את צורת העבודה
• בנוסף: נכשיר את התלמידים לקראת ראיון עבודה ונספק הערכת יכולות ומשוב בתחומים הנלמדים הן לתלמיד והן לחברות אשר יבקשו לקלוט את המסיימים

Duration:

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• לימוד של שפת תיאור חומרה: VHDL/Verilog – במשך 36 שעות נלמד את מבנה השפה בצורה יסודית ומעמיקה, נלמד כתיבה נכונה ויעילה, כל זאת תוך מימוש במעבדות מעשיות
• FPGA Design — לחלק זה הקצנו 52 שעות שבהן נלמד את המבנה הפנימי של הרכיבים, כיצד ניתן להשתמש במשאבים השונים של הרכיבים, כיצד לקרוא דוחות בצורה נכונה, הממשק בין הרכיב לכרטיס, השיקולים בעריכת כרטיס ועוד...
• הבנת מבנה שעונים פנימי בתוך ה — FPGA
• הבנת מורכבות תזמונים והדרך להתמודד עימם
• יכולת קריאה והבנה של דוחות זמנים של הכלים השונים והבנת צווארי הבקבוק של התכנון, וכיצד ניתן לשפר תזמונים ו/או מיקום על הרכיב
• הבנה מעמיקה של הארכיטקטורה הפנימית של רכיבי FPGA
• כלי פיתוח – לחלק זה הקצנו 12 שעות שבהם הסטודנט ייחשף לכלים שונים וילמד כיצד ניתן להשתמש בהם בצורה נכונה כדי לקבל ביצועים מיטביים. לימוד של כלי פיתוח נפוצים בארץ כמו: Synplicity, Precision, ISE, Quartos, Modelsim ועוד... 
• פרויקט מעשי – הפרויקט יהיה ברמה של התעשייה ומנחה מטעמינו ילווה את הסטודנט לכל אורך הפרויקט

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This two-day course shows how to perform various image processing techniques using the Image Processing Toolbox. The course explores the different types of image representations, how to enhance image characteristics, image filtering, and how to reduce the effects of noise and blurring in an image. It also introduces different methods used to extract features and objects within an image, image registration, and a few techniques for reconstructing images/objects.


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MATLAB Fundamentals is a three-day course that provides a comprehensive introduction to the MATLAB technical computing environment. This course is intended for beginning users and those looking for a review. No prior programming experience or knowledge of MATLAB is assumed, and the course is structured to allow thorough assimilation of ideas through hands-on examples and exercises. MATLAB competency is developed in a natural way, with an emphasis on practical application. Themes of data analysis, visualization, modeling, and programming are explored throughout the course. Topics Include:

• Working with the MATLAB user interface
• Entering commands and creating variables
• Performing analysis on vectors and matrices
• Visualizing vector and matrix data
• Working with data files
• Working with data types
• Automating commands with scripts
• Writing programs with logic and flow control
• Writing functions

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This course is for engineers who are new to system and algorithm modeling and design validation in Simulink®. It demonstrates how to apply basic modeling techniques and tools to develop Simulink block diagrams. Topics include:

• Creating and modifying Simulink models and simulate system dynamics
• Modeling continuous-time, discrete-time, and hybrid systems
• Modifying solver settings for simulation accuracy and speed
• Building hierarchy into a Simulink model
• Creating reusable model components using subsystems, libraries, and model references

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