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Hardware design has revolutionized the way the world interacts. Device capabilities continue to sky rocket today and designers must explore more ways to improve time to market. Debugging problems costs time and threatens stellar performance. Trial and error can push time to market to infinity and beyond.
Training fills the spaces between inefficiency and productivity. With Logtel high tech training, your engineers will find all the knowledge and skills necessary to go ahead and design the future. Advanced courses help you push the outer limits of the latest technologies. Logtel is also the Authorised Training Provider (ATP) in Israel and Turkey training Xilinx customers and partners.
Browse our variety of topics below. Logtel can also tailor-develop a training plan that fits your organization's current needs for the diverse background of your engineers. In-House sessions are offered to our clients on-site so you maintain your employee productivity throughout the training program. 'Public' training programs allow your selected employees starting from a single individual - to join training programs taking place at a Logtel training center.
* For more training opportunities, please check our Catalog or contact us for details.
| Course name | Coming Date | Duration (days) | More info | |||
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| FPGA TOOLS | ||||||
| Debugging Techniques using the ChipScope Pro tools | Call | 2 |
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As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug.
This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.
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| Designing FPGAs Using the Vivado Design Suite 1 | 08/11/19 | 2 |
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This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow.
For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered. LevelFPGA 1[Close] |
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| Designing FPGAs Using the Vivado Design Suite 2 | 29/10/19 | 3 |
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This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.
Level:FPGA 2[Close] |
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| Designing with the PlanAhead tool | Call | 3 |
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Learn to increase design performance and achieve repeatable results, plan an I/O pin layout, and implement by using the PlanAhead software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool, synthesis and project tips, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope Pro tool, and design preservation with partitions.
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| FPGA - Architecture and ISE Features | Call | 2 |
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ISE Design Tool Flow provides the overall context and framework for the development cycle of FPGAs. For those uninitiated to FPGA design, this course will arm you with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design now.
The flow will take you from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced. Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow. This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. [Close] |
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| ADVANCED FPGA | ||||||
| Debugging Techniques Using the Vivado Logic Analyzer | Call | 2 |
Click here
As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use Vivado® logic analyzer debug solution helps minimize the amount of time required for verification and debug.
This one-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the Vivado debug tool can address advanced verification and debugging challenges. Level:FPGA 2[Close] |
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| Designing for Performance | Call | 2 |
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Attending the Designing for Performance class will help you create more efficient FPGA designs. This course will enable you to optimize your design for usage in a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs. Level:FPGA3 [Close] |
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| Designing FPGAs Using the Vivado Design Suite 3 | Call | 3 |
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This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL
coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado logic analyzer. Level:FPGA 3[Close] |
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| Designing FPGAs Using the Vivado Design Suite 4 | 18/12/19 | 2 |
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| Designing with Multi-Gigabit Serial I/O | Call | 3 |
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Learn how to employ GTP and GTX serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Level: Connectivity 3 [Close] |
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| Designing with the Spartan-6 and Virtex-6 | Call | 3 |
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Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
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| Designing with the UltraScale and UltraScale+ Architectures | 28/10/19 | 2 |
Click here
This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale and UltraScale+ architectures. Targeted towards designers who have used the Vivado® Design Suite, this course focuses on designing for the new and enhanced resources found in our new FPGA families.
Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered. In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught. [Close] |
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| Designing with the Xilinx 7 Series | Call | 2 |
Click here
Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express® technology, analog to digital converters and gigabit transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
FPGA3 |
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| Designing with the Xilinx Analog Mixed Signal Solution | Call | 2 |
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This course introduces the Xilinx Agile Mixed Signal (AMS) solution and the appropriate tools and techniques for hardware engineers and analog engineers to utilize this solution. The complete front-to-back design flow is covered, including the evaluation of the Xilinx Analog-to-Digital Converter (XADC) block utilizing the KC705 board and the evaluator add-on card, the various ways to include the XADC in your design, XADC simulation of an analog input, viewing the digital output, and implementation. Additionally, labs are provided that support each topic, including the compete flow.
Level: FPGA 3 [Close] |
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| Designing with UltraScale FPGA Transceivers | Call | 2 |
Click here
Learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the UltraScale FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Level:Connectivity 3[Close] |
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| FPGA - Advanced Implementation | Call | 3 |
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Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools.
This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and 7 series FPGAs.
FPGA 4 |
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| FPGA - Migrating to Xilinx for experts | Call | 2 |
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This course focuses on providing ASIC/ FPGA experienced designers with the Xilinx tool-set flow. Current designers will get familiar with the various Xilinx tools, (ISE, XST, MAP, Place and Route, Trace…) and design techniques. HDL inference of FPGA resources and coding examples are provided. The course highlights the Virtex-IV family though most concepts can also be applied to Virtex-based designs. HDL inference of FPGA resources and coding examples are provided.
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| FPGA - Power Optimization | Call | 1 |
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Attending the FPGA Power Optimization class will help you create a more power efficient FPGA design. This course can help you fit your design into a smaller FPGA, reduce your FPGA’s power consumption, or run your FPGA at a lower temperature.
In addition, by mastering the tools and design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs. Level: FPGA 2 [Close] |
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| FPGA - Tips and Tricks for FPGA Designers | Call | 1 |
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Attending the Tips & Tricks for FPGA Design class will enrich your knowledge in several aspects of the FPGA design world. This 1 day seminar will enable you to get familiar with new aspects and problems you may encounter during your project flow. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, lower the design risk and development costs.
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| FPGA Design Methodology | Call | 1 |
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This course describes the FPGA design best practices and skills to be successful using the Vivado™ Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an FPGA design methodology case study. The full FPGA Design Methodology Checklist is also introduced.
Level:FPGA 3[Close] |
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| FPGA for Board Designers | 04/12/19 | 2 |
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| Industrial Motor Control Using FPGAs and SoCs | Call | 1 |
Click here
Learn how to implement motor control solutions using Xilinx All Programmable devices. This course requires basic knowledge of motor control; this comprehensive course covers motor control concepts; identifies the challenges in typical motor control solutions such as brushless direct current (DC), stepper, and permanent magnet synchronous motor (PMSM) motor control solutions and then demonstrates motor control techniques in Xilinx FPGAs and SoCs with the help of IPs provided by QDESYS.
Level:Application Specific[Close] |
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| UltraFast Design Methodology | Call | 1 |
Click here
This course describes the FPGA design best practices and skills to be successful using the Vivado® Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.
Level:FPGA 3[Close] |
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| UltraScale and UltraScale+ Architectures Workshop | Call | 1 |
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This is a one-day version of the Designing with the UltraScale Architecture course and introduces new and experienced designers to the most sophisticated aspects of the UltraScale™ and UltraScale+™ architectures. Targeted towards designers who have used the Vivado® Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family.
Topics covered include an introduction to the clock management resources (MMCM and PLL), global and regional clocking resources, memory resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered. In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught. Level:FPGA 3[Close] |
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| Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users | Call | 3 |
Click here
This course will update experienced ISE software users to utilize the Vivado Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design. Level:FPGA 2[Close] |
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| Vivado Design Suite Hands-on Introductory Workshop | Call | 1 |
Click here
This course offers introductory training on the Vivado® Design Suite. This course is for experienced ISE® software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx Design Constraints, and basic timing reports.
Level:FPGA 1[Close] |
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| Xilinx Partial Reconfiguration Tools & Techniques | Call | 2 |
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Learn how to construct, implement, and download a Partially Reconfigurable (PR) FPGA design using the Vivado® Design Suite. This course covers both the tool flow and mechanics of successfully creating a PR design.
The emphasis is on: Identifying best design practices and understanding the subtleties of the PR design flow Using the PR controller and PR decoupler IP in the PR process Implementing PR in an embedded system environment Applying appropriate debugging techniques on PR designs Employing best practice coding styles for a PR system * This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. ** The UltraScale architecture versions of the "Using the PRC IP in a Partial Reconfiguration Design" lab and the "Using ILA Cores to Debug Partial Reconfiguration Designs" lab are not available because of QSPI and PRC issues on the KCU105 board. These two labs support only the 7 series architecture. The "Partial Reconfiguration in Embedded Systems" lab requires a ZedBoard for implementation. After completing this comprehensive training, you will have the necessary skills to: ▪ Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices) ▪ Define PR regions and reconfigurable modules with the Vivado Design Suite ▪ Generate the appropriate full and partial bitstreams for a PR design ▪ Use the ICAP and PCAP components to deliver the partially reconfigurable systems ▪ Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs ▪ Implement a Partial Reconfiguration system using the following techniques: ○ Direct JTAG connection ○ Floorplanning ○ Timing constraints and analysis ▪ Implement a PR system using the PRC IP ▪ Implement a PR system in an embedded environment ▪ Debug PR designs [Close] |
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| HARDWARE DEFINITION LANGUAGES | ||||||
| Advanced Design with Verilog | Call | 2 |
Click here
This comprehensive 2 days course provides complete and integrated training program. It is structured as a comparison between traditional Verilog 1995 and newer Verilog standards – 1364-2001 and 1800-2005 System Verilog. The goal of this course is to fulfill needs and requirements engineers, who want to exploit wide breadth of System Verilog features for both design and basic testbench.
Intermediate to Advanced
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| Designing with Verilog | 06/11/19 | 4 |
Click here
This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. Level:FPGA 1[Close] |
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| Designing with VHDL | Call | 4 |
Click here
This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.
In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. Level: FPGA 1 [Close] |
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| Essential Tcl Scripting for the Vivado Design Suite | Call | 1 |
Click here
Learn how to use basic Tcl syntax and language structures to build scripts suitable for use with Xilinx FPGA design tools. Learn about the effective use of variables, data types, and Tcl constructs to build effective conditional statements and loop controls. You will also have the opportunity to use Tcl language constructs with several labs designed to provide you scripting experience within the Vivado™ Design Suite.
Level: FPGA 1 [Close] |
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| Fast-track Verilog for VHDL Users | Call | 2 |
Click here
Verilog for VHDL Users is an intensive 2-day course, converting knowledge of VHDL to practical Verilog skills.
Contrasting Verilog and VHDL, this course demonstrates similarities and highlights differences between two hardware description languages and their associated design flows. The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools. Labs comprise about 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. [Close] |
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| SystemVerilog for Design and Verification | Call | 4 |
Click here
This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs. After completing this comprehensive training, you will have the necessary skills to: ▪ Describe the features and benefits of using SystemVerilog for RTL design ▪ Identify the new data types supported in SystemVerilog ▪ Use an enumerated data type for coding a finite state machine (FSM) ▪ Explain how to use structures, unions, and arrays ▪ Describe the new procedural blocks and analyze the affected synthesis results ▪ Define the enhancements and ability to reuse tasks, functions, and packages ▪ Identify how to simplify module definitions and instantiations using interfaces ▪ Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis ▪ Target and optimize Xilinx FPGAs by using SystemVerilog ▪ Synthesize and analyze SystemVerilog designs with the Vivado Design Suite ▪ Download a complete SystemVerilog design to an evaluation ▪ Describe the advantages and enhancements to SystemVerilog to support verification ▪ Define the new data types available in SystemVerilog ▪ Analyze and use the improvements to tasks and functions ▪ Discuss and use the various new verification building blocks available in SystemVerilog ▪ Describe object-oriented programming and create a class-based verification environment ▪ Explain the various methods for creating random data ▪ Create and utilize random data for generating stimulus to a DUT ▪ Identify how SystemVerilog enhances functional coverage for simulation verification ▪ Utilize assertions to quickly identify correct behavior in simulation ▪ Identify how the direct programming interface can be used with C/C++ in a verification environment.
FPGA1
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| Verification with SystemVerilog | Call | 2 |
Click here
This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs. Level:FPGA 1[Close] |
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| VHDL - Advanced | Call | 2 |
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Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.
The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules. [Close] |
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| VHDL - Expert VHDL for Design and Verification | Call | 3 |
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VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies. [Close] |
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| Xilinx SystemVerilog for Design and Verification | Call | 4 |
Click here
This comprehensive 4-days hands-on intensive course provides complete and integrated training program. It provides the participants with a deep knowledge of 1800-2005 SystemVerilog. The goal of this course is to fulfill the needs and requirements of engineers wanting to exploit the breadth of SystemVerilog features for both design and verification.
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| DOULOS TRAINING | ||||||
| Comprehensive SystemVerilog | Call | 5 |
Click here
SystemVerilog (IEEE 1800™) is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture.
Comprehensive SystemVerilog provides a complete and integrated training program to fulfil the requirements of verification engineers and those wishing to evaluate SystemVerilog's applicability to both design and verification applications. It is structured to enable engineers to develop their skills to cover the full breadth of SystemVerilog features for both design and verification. This includes the requirements of verification engineers who wish to exploit the potential of class-based verification and object oriented techniques using SystemVerilog, as well as RTL coding, assertions and test benches. Design engineers who do not intend to use SystemVerilog for class-based verification should attend the shorter training course SystemVerilog for Designers, which shares the same content as Days 1 to 3 of Comprehensive SystemVerilog. Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. Level: Standard Level [Close] |
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| Doulos Advanced Design with VHDL | Call | 2 |
Click here
VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice. This training builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.
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| Doulos Fast-track Verilog for VHDL Users | Call | 2 |
Click here
Verilog for VHDL Users is an intensive 2-day course, converting knowledge of VHDL to practical Verilog skills.
Contrasting Verilog and VHDL, this course demonstrates similarities and highlights differences between two hardware description languages and their associated design flows. The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools. Labs comprise about 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. [Close] |
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| Doulos OVM Adopter Class | Call | 4 |
Click here
Course description with information on the course – marketing oriented.
Open Verification Methodology (OVM) is a non-proprietary functional verification methodology based on SystemVerilog. The source code and documentation are freely available under an open-source Apache license. OVM offers a complete framework for the creation of sophisticated functional verification environments in SystemVerilog, and encourages the development and deployment of re-usable verification components. It has comprehensive support for constrained random stimulus generation, including structured sequence generation, and for transaction-level modelling. OVM testbenches also support functional coverage collection and assertions. OVM exploits the object-oriented programming (or "class-based") features of SystemVerilog. The open structure, extensive automation, and standard transaction-level interfaces of OVM make it suitable for building functional verification environments ranging from simple block-level tests to the most complex coverage-driven testbenches. Delegates for this course must start with a detailed knowledge of building class-based verification environments using SystemVerilog. The course leads delegates through to full verification project readiness by focussing on the in-depth practical application of OVM using commercial verification tools such as Mentor Graphics Questa™Sim and Synopsys® VCS®. Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. During the hands-on workshops, delegates will build a complete OVM verification environment for a small example system. Level: Standard Level OVM Training [Close] |
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| Doulos SystemVerilog for Designers | Call | 3 |
Click here
SystemVerilog (IEEE 1800™) is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture.
SystemVerilog for Designers provides a compact and focused training program to fulfil the requirements of design groups. It is structured to enable designers to develop their capability by exploiting SystemVerilog features for mainstream design and verification requirements, including RTL coding, assertions and test benches. It is not intended to fulfil the deeper requirements of verification specialists who will wish to exploit the potential of class-based verification and object-oriented techniques using SystemVerilog. (Such requirements are covered in Days 4 and 5 of the Comprehensive SystemVerilog course, which includes the content of SystemVerilog for Designers as its first three days.) Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Level: Standard Level [Close] |
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| Doulos UVM Adopter Class | Call | 4 |
Click here
The Universal Verification Methodology (UVM) is a standard functional verification methodology for SystemVerilog, controlled by Accellera, and endorsed and supported by all major SystemVerilog simulator vendors. The source code and documentation are freely available under an open-source Apache license. UVM offers a complete framework for the creation of sophisticated functional verification environments in SystemVerilog, and encourages the development and deployment of re-usable verification components.
UVM has comprehensive support for constrained random stimulus generation, including structured sequence generation, and for transaction-level modeling. UVM testbenches also support functional coverage collection and assertions. UVM exploits the object-oriented programming (or "class-based") features of SystemVerilog. The open structure, extensive automation, and standard transaction-level interfaces of UVM make it suitable for building functional verification environments ranging from simple block-level tests to the most complex coverage-driven testbenches. Delegates for this course must start with a detailed knowledge of building class-based verification environments using SystemVerilog. The course leads delegates through to full verification project readiness by focusing on the in-depth practical application of UVM using commercial verification tools such as Cadence Incisive® Enterprise Simulator, Mentor Graphics Questa™Sim, and Synopsys® VCS®. Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. During the hands-on workshops, delegates will build a complete UVM verification environment for a small example system. [Close] |
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| SystemVerilog for FPGA/ASIC Design | Call | 4 |
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SystemVerilog for FPGA/ASIC Design prepares the engineer for practical project readiness for FPGA or ASIC design, including RTL synthesis, block-level test benches, and FPGA design flows. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. While the emphasis is on the practical SystemVerilog-to-hardware flow for FPGA devices, this training course also provides the essential foundation needed by ASIC and FPGA designers wishing to go on to use the advanced features of SystemVerilog for functional verification.
SystemVerilog for FPGA/ASIC Design is suitable for delegates who are learning SystemVerilog as their first hardware description language. For teams who are already skilled in Verilog or VHDL, this training course can be offered in a shortened form for on-site delivery. For verification teams who are looking to use the class-based features of SystemVerilog for constrained random functional verification, Logtel provides Modular SystemVerilog for in-house training options. Because Logtel is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. Level: Standard Level [Close] |
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| SystemVerilog for Verification Specialists | Call | 4 |
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SystemVerilog (IEEE 1800™) is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture.
SystemVerilog for Verification Specialists provides a 4 day training program to fulfil the requirements of verification engineers or those wishing to evaluate SystemVerilog's applicability for complex verification application. It is structured to enable engineers to develop their skills to utilise the full breadth of SystemVerilog features for verification. This includes how to exploit the potential of class-based verification and object oriented techniques using SystemVerilog, as well as application for standard test bench development and module-based verification. The course assumes Verilog knowledge but no prior SystemVerilog knowledge. VHDL users preparing to use SystemVerilog should consider preparatory training with the 2 day Fast Track Verilog for VHDL Users. The course includes an introduction to UVM (and OVM) but full scope project readiness in UVM requires follow-on training with the 3 day UVM Adopter Class. Design engineers (FPGA or ASIC) who intend to use SystemVerilog for RTL design and basic test bench development should attend the companion training course SystemVerilog for FPGA/ASIC Design. Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Level: Standard Level [Close] |
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| VHDL - Doulos Expert for Design and Verification | Call | 3 |
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VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies. [Close] |
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| VHDL - For Designers | Call | 4 |
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VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
This trainingprepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. [Close] |
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| VMM Adopter Class | Call | 2 |
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The Verification Methodology Manual for SystemVerilog (VMM) specifies a functional verification methodology, and defines the VMM Standard Library implemented in SystemVerilog. VMM includes constrained random stimulus generation, functional coverage collection, assertions, and transaction-level modelling. VMM's layered structure and channel-based communication model make it suitable for building both very simple and very complex functional verification environments.
Delegates for this course must start with a working knowledge of SystemVerilog, including its object-oriented programming (class-based) features. This course takes delegates through to full VMM verification project readiness by focussing on the verification principles and the in-depth practical application of the VMM. Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. In the hands-on workshops, delegates will progressively build a complete VMM verification environment for a small example system. Level: Advanced Level [Close] |
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| EMBEDDED DESIGN | ||||||
| Advanced Features and Techniques of Embedded Systems Design | Call | 1 |
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Advanced Features and Techniques of Embedded Systems Design provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Vivado™ IP Integrator. This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system in the Zynq™ All Programmable System on a Chip (SoC) or Microblaze™ soft processor.
This course builds on the skills gained in the Embedded Systems Design course. Labs provide hands-on experience with developing, debugging, and simulating an embedded system. Utilizing memory resources and implementing high-performance DMA are also covered. Labs use demo boards in which designs are downloaded and verified. Level:Embedded Hardware 4[Close] |
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| Advanced Features and Techniques of Embedded Systems Software Design | Call | 1 |
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This course will help software engineers fully utilize the components available in the Zynq® All Programmable System on a Chip (SoC) processing system (PS). This course covers advanced Zynq All Programmable SoC topics for the software engineer, including advanced boot methodology, the NEON co-processor, programming PS system-level function control registers, the general interrupt controller, the DMA, Ethernet, and USB controllers, and the various low-speed peripherals included in the Zynq All Programmable SoC processing system.
Level:Embedded Software 4[Close] |
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| Advanced SDSoC Development Environment and Methodology | Call | 2 |
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This two-day course is structured to help designers employ SDSoC™ development environment optimization techniques to create high-performance, accelerated systems. The focus is on optimizing memory access and hardware functions, generating C-callable IP libraries, and creating custom platforms. The course also includes an introduction to the Xilinx reVISION Stack.
Level:Embedded 3[Close] |
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| C Language Programming with SDK | Call | 2 |
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This course is broken into a day of C language review, including variable naming, usage, and modifiers as well as an introduction to the Software Development Kit (SDK) environment, an explanation of the use of the preprocessors, program control, and proper use of functions. The second day consists of common issues and techniques employed by embedded programmers in the Xilinx SDK environment. This comprehensive course equally balances lecture modules with practical hands-on lab work.
Level: Embedded 1 [Close] |
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| Developing and Optimizing Applications Using the OpenCL Framework for FPGAs | Call | 2 |
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Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel™ development environment for use on Xilinx FPGAs. Porting existing applications is also covered.
This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources. Level:SDx 2[Close] |
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| Developing AWS F1 Applications Using the SDAccel Environment | Call | 1 |
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This one-day course is structured to help designers new to the Amazon Web Services (AWS) F1 instance quickly understand the complete flow of design generation for AWS F1. The focus is on utilizing the tools to accelerate a design at the system architecture level and the optimization of the accelerators.
Level: Embedded 2Training Duration: 1 day[Close] |
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| Embedded C/C++ SDSoC Development Environment and Methodology | 27/12/19 | 1 |
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This one-day course is structured to help designers new to the SDSoC™ development environment to quickly create accelerated systems. The focus is on utilizing the tools to accelerate an existing design at the system architecture level, not on the optimization of the accelerator microarchitectures.
Several optional modules are provided to quickly provide students with the necessary background on both hardware and software. The first half of this class is Level 1 while the afternoon's topics are at Level 2. . [Close] |
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| Embedded Design with PetaLinux SDK | Call | 2 |
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This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded PetaLinux SDK operating system on a Xilinx Zynq™ All Programmable System on a Chip (SoC) processor development board. The course offers students hands-on experience on building the environment and booting the system using a basic Zynq All Programmable SoC design with PetaLinux SDK on the ARM® Cortex™-A9 processor.
This course also introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging/profiling options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow.
Level:
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| Embedded Systems Design | 13/11/19 | 3 |
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This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado Design Suite. The features and capabilities of both the Zynq All Programmable System on a Chip (SoC), Zynq UltraScale+ MPSoC, and the MicroBlaze™ soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.
The Xilinx Zynq families enable a new level of system design capabilities over previous embedded technologies, which is highlighted throughout the course. Level:Embedded Hardware 3 [Close] |
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| Embedded Systems Software Design | Call | 3 |
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This course introduces you to software design and development for the Xilinx Zynq® All Programmable System on a Chip (SoC) and Zynq UltraScale+ MPSoC devices using the Xilinx Software Development Kit (SDK). You will learn the concepts, tools, and techniques required for the software phase of the design cycle.
Embedded Software 3 |
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| Essentials of Microprocessors | 23/10/19 | 2 |
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Learn what makes microprocessors tick! This class offers insights into all major aspects of microprocessors, from registers through coprocessors and everything in between. Differences between RISC and CISC architectures are explored as well as the concept of interrupts. A generic microprocessor is programmed and run in simulation to reinforce the principles learned in the lecture modules. The student will leave the class well prepared for the Xilinx Zynq training curriculum.
Embedded 1 |
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| Freescale - P204X QorIQ implementation | Call | 6 | ||||
| Neon Programming | Call | 2 | ||||
| SDSoC Development Environment and Methodology | Call | 1 |
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This one-day course is structured to help designers new to the SDSoC™ development environment to quickly understand the full "end-user" tool flow to create accelerated systems. The focus is on utilizing the tools to accelerate an existing design at the system architecture level, not on the optimization of the accelerator microarchitectures.
Several optional modules are provided to quickly provide students with the necessary background on both hardware and software. [Close] |
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| Zynq All Programmable SoC Accelerators | Call | 1 |
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Custom processor accelerators are quickly becoming standard practice for reaching system performance goals. This one-day introduction to the accelerator development flow focuses on how to measure system performance, determine what software functionality should be moved to hardware, how to assemble a custom accelerator using the Vivado® HLS tool, add the custom accelerator to a Zynq® All Programmable SoC design, and finally measure accelerated performance.
Emphasis is placed on the Zynq AP SoC's architectural features that make coupling an accelerator to the multi-processor core a possibility as well as the many techniques for implementing accelerated systems. Discussion of typical tradeoffs that a system architect will likely make is also included. The specifics of the accelerator itself is secondary as the focus is on how to integrate an accelerator rather than accelerator design techniques. Level:Embedded 2[Close] |
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| Zynq All Programmable SoC System Architecture | 26/09/19 | 3 |
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The Xilinx Zynq® All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq All Programmable SoC.
This course presents the features and benefits of the Zynq architecture for making decisions on how to best architect a Zynq All Programmable SoC project. It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq All Programmable SoC.The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL. Level:Embedded Hardware 3[Close] |
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| Zynq Smarter Solutions – Decision Maker 1/2 Day and 1 Day Seminars | Call | 1 |
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The half-day and one-day seminars will focus on some key challenges commonly encountered in developing embedded systems and how using the Zynq®-7000 All Programmable SoC (AP SoC) devices allays many of these situations.
The seminars are equally designed for networking, vision, and generic designers to help them identify their challenges and discover why Zynq-7000 devices are the right fit for their applications. The seminars and demos will also help students choose the appropriate path in the Zynq Smarter Solutions Workshop [Close] |
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| Zynq Smarter Solutions – Hardware Workshop | Call | 1 |
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This one-day workshop quickly introduces you to developing embedded systems using the Vivado® Design Suite. The focus is on the basic features and capabilities of the Zynq® All Programmable System on a Chip (SoC), as well as tools and techniques.
The hands-on labs provide students the experience of designing, expanding, and debugging an embedded system, creating and importing a custom AXI4 peripheral, and performing bus functional model simulation. [Close] |
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| Zynq Smarter Solutions – Software Workshop | Call | 1 |
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This one-day workshop introduces you to software design and development for the Zynq® All Programmable System on a Chip (SoC) using the Xilinx Software Development Kit (SDK). The focus is on the basic features and capabilities of the Zynq All Programmable SoC as well as the tools and techniques required for the software phase of the design cycle.
The hands-on labs provide students experience with the design and implementation of the software application and the board support package (BSP) for resource access and management of the Xilinx Standalone library. Labs also include debugging a remote server Linux application, profiling for performance, and interrupts. [Close] |
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| Zynq UltraScale+ MPSoC for the Hardware Designer | Call | 2 |
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| Zynq UltraScale+ MPSoC for the Software Developer | 19/11/19 | 2 |
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This two-day course is structured to provide software developers with a catalog of OS implementation options, including hypervisors, various Linux implementations, booting and configuring a system, and power management for the Zynq® UltraScale+™ MPSoC family.
Level:Embedded Software 3[Close] |
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| Zynq UltraScale+ MPSoC for the System Architect | Call | 2 |
Click here
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| ARM | ||||||
| ARM - AXI3 / AXI4 INTERCONNECT | Call | 2 |
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AXI v4 is the interconnect used by Cortex-A and Cortex-R ARM CPUs, see the outlines of these courses
Course objectives:• This course details first the AXI3 protocol • New signals present in AXI4 are then described • The course explains the AXI4 stream protocol and indicates in which case this simplified protocol is suitable • AXI4-lite protocol is described • The NIC-301 interconnect IP is studied, clarifying synthesis options as well as software QOS parameterizing • AXI Coherency Extensions (ACE) new channels are explained through an overall introduction to snooping • The CCI-400 interconnect IP is described, highlighting the purpose of ACE-lite ports [Close] |
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| ARM - CORTEX-A15 / CORTEX-A7 BIG/Little Implementation | Call | 4 | ||||
| ARM - CORTEX-A53 IMPLEMENTATION - ARM ARCHITECTURE V8 | Call | 4 | ||||
| ARM - CORTEX-A57 IMPLEMENTATION - ARM ARCHITECTURE V8 | Call | 4 | ||||
| ARM - CORTEX-A8 SYSTEM DESIGN | Call | 3 | ||||
| ARM - CORTEX-A9MP SOFTWARE IMPLEMENTATION | Call | 3 | ||||
| ARM - CYCLONE-V CORTEX-A9 HARD PROCESSOR SYSTEM | Call | 5 | ||||
| ARM CORTEX-A9MP SYSTEM DESIGN | Call | 4 |
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This course takes an in depth look at the considerations you will need to take into account when designing a system containing a Cortex-A9 core
It is aimed at: Software engineers who not only want to obtain details of how to write software to run on the Cortex-A9, but also wish to obtain an understanding of hardware design issues Hardware engineers who need to understand how to design Cortex-A9 based systems, but also wish to obtain an understanding of the issues of writing software to run on that system. Level: Intermediate [Close] |
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| ARM CORTEX-R52 | Call | 4 |
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This course aims to explain the architecture of the ARM Cortex-R52 to enable participants to efficiently design a SoC based on this CPU and develop low level software. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the V8-R specification. They will study the mechanisms specific to ARM V8-R processors, particularly caches, TCMs and MPU. Labs contribute to become familiar with V8-R programming.
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| DSP DESIGN | ||||||
| C-based Design: High-Level Synthesis with the Vivado HLx Tool | Call | 3 |
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The course provides a thorough introduction to the Vivado® High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.
Level: DSP 3[Close] |
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| C-based HLS Coding for Hardware Designers | Call | 1 |
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C-based coding is increasingly used for the modeling and high-level synthesis of hardware components. This course provides hardware engineers with sufficient knowledge of C-programming techniques for Vivado™ HLS to take advantage of Xilinx FPGAs. Learn high-level synthesis best practices, methodology, and subtleties of C-based coding for hardware modeling, synthesis, and verification.
Level: DSP 3 [Close] |
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| C-based HLS Coding for Software Designers | Call | 1 |
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C-based coding is increasingly used for the modeling and high-level synthesis of hardware components. This course provides software engineers with sufficient knowledge of FPGA hardware to efficiently code for high-level synthesis. Learn the high-level synthesis best practices, methodology, and subtleties of C-based coding for hardware modeling, synthesis, and verification.
Level: DSP 3 [Close] |
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| DSP Design Using System Generator | Call | 2 |
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This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.
DSP 3
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| Essential DSP Implementation Techniques for Xilinx FPGAs | Call | 2 |
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This course provides a foundation for Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced. The course is complemented by hands-on exercises to reinforce the concepts learned.
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| How to Design a Xilinx Digital Signal Processing System in 1 Day | Call | 1 |
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The workshop introduces you to fundamental DSP concepts, algorithms, and techniques for implementation in Xilinx FPGAs. Design examples and labs are drawn from several common applications spaces, including wireless communications, video, and imaging.
Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses. The material is also complementary to the Avnet SpeedWay Design Workshop on FPGA-Based System Design with High-Speed Data Converters. Level: DSP 3 [Close] |
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| Signal Processing Applications and Algorithms | Call | 3 |
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Attending the Signal Processing Applications and Algorithms class will give you a theoretical background on Signal Processing Algorithms and demonstrates Applications used in the industry. You will be mastering the MATLAB® and Simulink® tools during the training in the lab exercises embedded into the training
[Close] |
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| VLSI-DSP for the ASIC and FPGA Engineer | Call | 3 |
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Many applications in today's technological world require fast DSP processing. Anything from physical layer processing in communication infrastructure to extraordinary image and sound processing in medical equipment. DSP is a unique area in VLSI design. There are many ways to implement the same DSP algorithm, though the efficient implementation may not be so obvious and would usually require particular expertise.The course introduces important basic concepts in DSP designing, surveys a variety of structures and advanced DSP implementations in VLSI. Level:Intermediate [Close] |
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| PCB WORLD | ||||||
| Advanced PCI Express | Call | 1 |
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This course introduces and details PCIe new features as introduced in PCIe versions 2.1 and 3.0.
Each new topic is presented from four different perspectives: - Motivation - Implementation - Configuration - Example. This is an in-depth course and is both hardware and software oriented. It describes the different options and discusses performance. It is also useful when determining system architecture. The course is based on well-known PCIe basics (as covered in the basic PCIe course at Logtel) [Close] |
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| Designing an Integrated PCI Express System | Call | 2 |
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Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.
Level:Connectivity 3[Close] |
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| Designing with PCI Express Gen 1.x – 4.0 | Call | 4 |
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The course provides a detailed and comprehensive understanding of the PCI Express technology.
The course is fully up-to-date and supports the basic and latest version of the international specification (1.x - 4.0), and covers all aspects of the specification from a hardware design perspective and also discusses the software requirements of PCI Express implementations. This course provides example implementations, and practical guidance that will give a running start on your design. [Close] |
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| Designing with the Ethernet Mac controllers | Call | 2 |
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Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements. Become familiar with Ethernet IP core design architectures, core IP port naming conventions, and signal waveforms.
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| Designing with the Zynq UltraScale+ RFSoC | Call | 2 |
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This course is structured to provide designers with an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family. Special emphasis is placed on the Data Converter and Soft-Decision FEC blocks.
Power estimation is covered to help designers identify the power demands of the device in various operating modes. Since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device, proper layout and PCB considerations are also covered. [Close] |
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| Designing with UltraScale FPGA Transceivers | Call | 2 |
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Learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the UltraScale FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
[Close] |
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| Designing with Xilinx Serial Transceivers | Call | 2 |
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In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs. Level:Connectivity 3[Close] |
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| EMI, EMC and ESD | Call | 3 |
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In modern electronics, component size continues to decrease and complexity to increase. Electrostatic and magnetic fields and their interactions are becoming increasingly important. As problems have arisen, creative solutions had to be developed. An understanding of the principles and developments in this growing field is essential to many individuals in electronics industries
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| FPGA for Board Designers | Call | 2 |
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| High-Speed Implementation and Simulation of DDR3 Interfaces | Call | 2 |
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This workshop is aimed at developers who want to implement high-speed interfaces between semiconductor components and who want to design complex high-speed circuits at board level. This Workshop is designed for developers who not only design schematics but also systems and the layout.
You will learn to judge when signal integrity is important and relevant, to interpret, for example, IBIS models, and to select appropriate termination procedures. Signal refection and crosstalk effects are described and demonstrated by simulation. Simulation examples are for typical PCB structures. You will learn how to implement high-speed buses, including clock design, loading and signal termination. Furthermore, the power distribution and bypassing design are main topics. Detailed discussion of solving potential Signal Integrity problems on high-speed memory interfaces and serial transceiver links (optional modules). [Close] |
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| How to Design a High-Speed Memory Interface | Call | 2 |
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This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs.
Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces. The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR, and QDRII+. Labs are available for DDR3 on the Kintex™-7 FPGA KC705 board.
Connectivity 3 |
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| How to Design a Xilinx Connectivity System in 1 Day | Call | 1 |
Click here
This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of serial transceivers, PCIe® technology, memory interfaces, and Ethernet MACs. Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses. Design examples and labs show components from the Connectivity Targeted Reference Design (TRD). In addition, an IBERT lab is available that highlights the usage of the serial transceivers.
Connectivity 2 |
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| How to Design High-Speed Interfaces | Call | 4 |
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Course Description
Are you interested in learning how to effectively utilize 7 series high-speed interface resources? This course supports both experienced and less experienced FPGA designers who have in minimum general digital hardware knowledge and basic information on 7 series FPGAs. Furthermore, first work with the new Xilinx VIVADO Design Suite is helpful. This course focuses on understanding as well as how to properly design for the high-speed interface solutions found in the new device families: transceiver in general, PCI Express and memory interfacing complemented with board design issues. Topics covered include interface overviews, design usage, simulation, implementation and examples on real hardware. This course also includes a detailed discussion about proper PCB design techniques that enables designers to avoid common mistakes and get the most out of their FPGA interfaces. A combination of modules and labs allow for practical hands-on application of the principles taught. [Close] |
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| Multi-Gigabit High Speed Design Using HyperLynx | Call | 2 |
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Learn when and how to apply signal integrity techniques to high-speed interfaces between FPGAs and/or other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed routing and clock design, including transmission line termination, loading, and jitter. You will gain the understanding of Multi-Gigabit serial Transceivers TX & RX architectures and operation though a deep dive in to Xilinx GTH & GTY High-speed Serial Transceivers.
You will work with S-parameters, IBIS & IBIS-AMI models and complete Pre-layout and Post-layout simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects, on-chip termination and TX/RX equalization. This course balances lecture modules with instructor demonstrations and practical hands-on labs. Level:Connectivity 3[Close] |
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| PCB Layout Design | Call | 4 |
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Good PCB (Printed Circuits Board) layout design plays a major role in electronic devices. Smart phones, I-Pad, laptops and many micro devises includes high density and high speed electronic boards.
This training will enable the electronic design engineer to enhance the electronic board performance by understanding and considering the PCB design technologies and requirements while in the schematic design phase. Practical Engineers and Electronic Engineers who would like to enter the magnificent world of PCB layout design are welcome to participate this training in order to give you the life opportunity to become a layout designers. This training includes all aspects of PCB layout design starting from define the electronic constrains, build components footprints, smart 3D components placement in the PCB area , understanding PCB technologies, sophisticated traces routing methods & high speed routing, invoking PCB production files and understanding GERBERS formats. [Close] |
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| PCIe Gen1.X to 4.X | Call | 4 |
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PCI Express is the open standards- based successor to PCI and its variants for server- and client-system I/O interconnects. Unlike PCI and PCI-X, which are based on 32- and 64-bit parallel buses, PCI Express uses high-speed serial link technology similar to that found in Gigabit Ethernet, Serial ATA (SATA), and Serial-Attached SCSI (SAS). PCI Express reflects an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses.
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| PCIe Protocol Overview | Call | 1 |
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This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.
Implementation issues are covered in the two-day Designing a LogiCORE PCI Express System course. Level:Connectivity 2[Close] |
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| Power & Signal Integrity for Board Design | Call | 3 |
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Learn when and how to apply power & signal integrity techniques to high-speed interfaces between components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
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| Signal Integrity and Board Design Using HyperLynx | 17/11/19 | 3 |
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Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
Connectivity 3 |
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| Tips & Tricks For Board Designers | Call | 1 |
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Attending the Tips & Tricks for Board Design class will enrich your knowledge in several features of current board design. This 1 day seminar will familiarize you with new aspects and problems you may encounter during project development. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to design faster, shorten development time, lower development costs and lower design risk.
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| Zynq Board Design and High-Speed Interfacing | Call | 2 |
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Are you interested in learning how to effectively utilize Zynq-7000 SoC high-speed interface resources? This course supports both experienced and less experienced designers who have in minimum general digital hardware knowledge and basic information on Zynq devices. Furthermore, first work with the new Xilinx VIVADO Design Suite is helpful. This course focuses on understanding as well as how to properly design for the high-speed interface solutions found in the new device families: transceiver in general, PCI Express and memory interfacing complemented with board design issues. Topics covered include interface overviews, design usage, simulation, implementation and examples on real hardware.
This course also includes a detailed discussion about proper PCB design techniques that enables designers to avoid common mistakes and get the most out of their FPGA interfaces. A combination of modules and labs allow for practical hands-on application of the principles taught. [Close] |
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| HARDWARE ENRICHMENT | ||||||
| ASIC Prototyping with FPGA | Call | 2 |
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The process of ASIC design and production becomes more and more expensive.
NRE may be millions of $$. Time to market is always critical and cycle needed to be shorter. Although good verification environment is essential for ASIC success, it may not be enough. Due to very long simulation cycle times , lack of manpower , timing issues , uncovered system scenarios , lack of software drivers etc. ASIC prototyping in FPGA increases significantly the probability of ASIC 1st time pass. However, there are technology differences between ASIC and FPGA that should be taken into consideration. This course will emphasize the differences and how they should be handled [Close] |
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| From Network Concept to Working Silicon | Call | 2 |
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Over the years the use of communication networks has not only increased but also changed dramatically. Carriers today are aiming for a converged network that will supply data, audio and video communication on the same network infrastructure, providing a wide variety of new applications alongside the classical telephony, internet surfing, and TV broadcasting. To meet that goal the routers and switches in these networks and their underlying HW engines must improve. The HW engines are required to do diverse tasks from parsing and editing the packets, through forwarding them to scheduling them. Applying the right mechanisms for these diverse, demanding tasks requires an understanding in both networking and chip design. This course will discuss the context between the two fields with samples of Xilinx' implementations.
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| Practical Aspects of Electronic Module Development & Production Workshop | Call | 1 |
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Introduction to all Electronic Module Development Variables and there Implication on the product design, for:
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| Principles of Digital Image Processing | Call | 4 |
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| RTOS & VxWorks | Call | 5 |
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| The Secrets of Electronics in two days | Call | 2 |
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This course presents the essentials of Electronics engineering and Hardware Design for software engineers. The course is a complete tour of the fundamentals of electrical engineering. It will enable the software engineer that works with an electronics engineer’s better communicate and understand the electrical engineering when working on a common project. The course presents examples of all the learning material.
Fundamental
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| USB Architecture | 16/11/19 | 2 |
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The purpose of this course is to provide the student with the theoretical knowledge required for defining and implementing systems based on USB versions 2, 3.0, 3.1, USB Type C.
The course begins with basic concepts and then fully describes in detail USB Architecture (USB2.0 & USB 3.0). The material is fully up-to-date and supports the latest version of the international specification. The course covers partially also OTG, UTMI + ULPI, LPM, HSIC and USB 3.1. During the course there are many examples which cover all aspects of USB specification
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| LONG TERM TRAINING (LTT) | ||||||
| Blockchain Xpert | Call |
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Teaching goals: The blockchain environment is constantly in flux, with rapid innovation changing the tools, ecosystem and most popular technologies often.
Through the currently most established ecosystems, you will learn the tools and mindset to quickly master new knowledge in the blockchain space. Duration: 30 Hours[Close] |
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| BoardDesignExpert (Haifa) | Call |
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Duration:
120 Hours
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| BoardDesignExpert (Petah Tikva) | Call |
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Duration:
120 Hours
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| FPGA Premium | Call |
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In this modular course we will execute end to end 2-4 projects that require the latest knowledge in FPGA design. The student will be able to choose a minimum of 2 projects that he would like to attend.
Each project will be presented to the student and will be guided by a top talented team that exist today in the FPGA industry, each lecture brings with him 20 years or more of FPGA design and at least 10 years of lecturing capabilities in FPGA. The student will present the project during the class and will be scored upon each project. FPGA Premium:The Hardware industry is all focused on the future technologies which are exploding these dates: cloud ouering, fastest data center, IOT, 5G and more…All those technologies will be and already being supported by cutting edge Hardware development. As an example- AMAZON decision of building a FPGA cloud service. As a results of those changes, hardware engineers have to deal with new capabilities in the FPGA world: * Fast interconnect such as PCIe Gen 3 / Gen 4. * Using HLS for faster development cycle to be adequate with the dev-ops environments. * Highest memory interfaces - DDR4. * Advanced chip as MPSoC, using ARM base solution with FPGA speed. As part of this urgent need, LOGTEL has built this exceptional workshop that will deeply focus on the cutting edge technologies of the hardware industry. Objetive:The course objective is to take FPGA experience engineers to the next level in their career and expertise.Type of Course:WorkshopDuration:40 hours8 meetings of 5 hours each- afternoon training. [Close] |
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| FPGAXpert | Call |
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Duration:
120 Hours
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| LinuXpert | Call |
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בקורס נכסה את כל מרחב ה-Linux עבור שלושת הרמות של מפתח ה-Linux כגון:
מהנדס SYSTEM/ מנהל IT: כתיבה של שפות Script ואיפיון מערכות מפתח User-Space : כתיבה במערכות קבצים שונות ואיפיון ארכיטקטוני ביניהם, כתיבה יעילה ונכונה עבור סביבות מרובות Thread ומעבדים. מפתח Kernel: כתיבה בתוך מערכת ההפעלה כגון עליית מערכות עם מיקוד בעולם הEmbedded-, הקצאות זיכרון וניהול נכון של זיכרון בין מרחבי המעבדים ושל Interrupt ותיזמונים.
Duration: 120 Hours[Close] |
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| MATLAB | ||||||
| Matlab - Advanced | Call | 2 |
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This two-day course shows attendees how to analyze signals and design signal processing systems using MATLAB® and Signal Processing Toolbox™. Parts of the course will also use Filter Design Toolbox™.
Topics include:
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| Matlab - Image Processing | Call | 2 |
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This two-day course shows how to perform various image processing techniques using the Image Processing Toolbox. The course explores the different types of image representations, how to enhance image characteristics, image filtering, and how to reduce the effects of noise and blurring in an image. It also introduces different methods used to extract features and objects within an image, image registration, and a few techniques for reconstructing images/objects.
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| MATLAB for Signal Processing | Call | 2 |
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This two-day course shows attendees how to analyze signals and design signal processing systems using MATLAB® and Signal Processing Toolbox™. Parts of the course will also use Filter Design Toolbox™.
Topics include:
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| MATLAB Fundamentals | Call | 3 |
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MATLAB Fundamentals is a three-day course that provides a comprehensive introduction to the MATLAB technical computing environment. This course is intended for beginning users and those looking for a review. No prior programming experience or knowledge of MATLAB is assumed, and the course is structured to allow thorough assimilation of ideas through hands-on examples and exercises. MATLAB competency is developed in a natural way, with an emphasis on practical application. Themes of data analysis, visualization, modeling, and programming are explored throughout the course. Topics Include:
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| Simulink for Communication Systems | Call | 1 |
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Using hands-on examples, this one-day course demonstrates the use of MathWorks products to design common communication systems. The emphasis is on designing end-to-end communication systems using Simulink®, Communications Blockset™, and Signal Processing Blockset™. Topics include:
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| Simulink for System and Algorithm Modeling | Call | 2 |
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This course is for engineers who are new to system and algorithm modeling and design validation in Simulink®. It demonstrates how to apply basic modeling techniques and tools to develop Simulink block diagrams. Topics include:
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| SPECIAL BUNDLES | ||||||
| FPGA in 7 days | Call | 7 | ||||
| System Verilog for VHDL Users | Call | 6 | ||||
| UVM for VHDL | Call | 9 | ||||
| Vivado in 4 days for ISE users | Call | 4 | ||||
| Vivado in 6 days | Call | 6 | ||||
| Zynq in 6 days for HW designers | Call | 6 | ||||
Logtel (c) All rights reserved 2010-2011 | Logtel Computer Communications LTD. | Developed by: Hagit Bagno | Designed: NotFromHere