HARDWARE

Advanced FPGA Implementation

Nº 533
DATE: CALL Other available dates:
PRICE NIS: 3780 + VAT /9 Tcs
DURATION: 3 Days

Course Overview:

Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this three-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.

Level:

FPGA 4

Who should attend?

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

Prerequisities:

Essentials of FPGA Design
Designing for Performance
Intermediate knowledge of Verilog or VHDL is strongly recommended
At least six months of design experience with Xilinx tools and FPGAs

Software Tools:

Xilinx ISE Design Suite: Logic or System Edition 13.1

Hardware

Architecture: Spartan-6 and Virtex-6 FPGAs
Demo board: Spartan-6 FPGA SP605 board

Skills Gained:

After completing this training, you will be able to:

Create and edit a User Constraint File (UCF)
Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfaces
Implement designs via the Tcl command line
Use the PlanAhead™ tool to create area constraints
Use design preservation techniques to simplify design ripple effects
Change signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor

Course Outline:

1. Introduction
Lab 1: Timing Closure Review

2. UCF Editing
Lab 2: UCF Editing

3. Advanced I/O Timing
Lab 3: Advanced I/O Timing

4. Tcl Scripting
Lab 4: Tcl Scripting

5. Floorplanning an Effective Layout
Lab 5: Floorplanning

6. Design Preservation Techniques
Lab 6: Leveraging Design Preservation for Predictable Results

7. FPGA Editor: Viewing and Editing a Routed Design
Lab 7: Advanced FPGA Editor

Lab Descriptions

Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.

Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.

Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.

Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.

Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.

Lab 6: Leveraging Design Preservation for Predictable Results – Utilize partitions to preserve timing results from one iteration to the next.

Lab 7: FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.

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