HARDWARE
Designing with Multi-Gigabit Serial I/O
Nº
551
DATE: CALL
PRICE NIS: 3780 + VAT /9 Tcs
DURATION: 3 Days
DATE: CALL
PRICE NIS: 3780 + VAT /9 Tcs
DURATION: 3 Days
Course Overview:
Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT FPGA or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Level:
Advanced
Who should attend?
FPGA designers and logic designers
Prerequisities:
- Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
- Familiarity with logic design (state machines and synchronous design)
- Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Software Tools
- Xilinx ISE Design Suite: System Edition 13.1
- ChipScope Pro software 13.1
- Mentor Graphics ModelSim simulator
Hardware
- Architecture: Spartan-6 and Virtex-6 FPGAs
- Demo board: Spartan-6 FPGA SP605 board
Skills Gained:
After completing this training, you will be able to:
- Describe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGA
-
Effectively utilize the following features of the GTP/GTX:
- 8B/10B and other encoding/decoding, comma detection, clock correction, and channel bonding
- Pre-emphasis and linear equalization
- Use the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a design
- Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design
Course Outline:
1. Course Agenda and Introduction
2. Spartan-6 and Virtex-6 Family Overview
3. Transceiver Overview
4. Transceiver Clocking and Resets
5. 8B/10B Encoder and Decoder
Lab 1: 8B/10B Disparity and Bypass
6. Commas and Deserializer Alignment
Lab 2:Commas and Data Alignment
7. RX Elastic Buffer and Clock Correction
Lab 3:Clock Correction
8. Channel Bonding
Lab 4:Channel Bonding
9. GTP Wizard Overview
Lab 5:GTP Core Generation
10. Transceiver Implementation and Simulation
Lab 6: Implementation and Simulation
11. Physical Media Attachments
12. Virtex-6 FPGA 64B/66B Encoding and the Gearbox
Lab 7:GTX 64B/66B Encoding
13. Transceiver Board Design
14. Transceiver Test and Debugging
15. RocketIO Transceiver Test and Debugging
Lab 8:System Lab or IBERT Lab Using Xilinx Boards
16. Transceiver Application Examples
2. Spartan-6 and Virtex-6 Family Overview
3. Transceiver Overview
4. Transceiver Clocking and Resets
5. 8B/10B Encoder and Decoder
Lab 1: 8B/10B Disparity and Bypass
6. Commas and Deserializer Alignment
Lab 2:Commas and Data Alignment
7. RX Elastic Buffer and Clock Correction
Lab 3:Clock Correction
8. Channel Bonding
Lab 4:Channel Bonding
9. GTP Wizard Overview
Lab 5:GTP Core Generation
10. Transceiver Implementation and Simulation
Lab 6: Implementation and Simulation
11. Physical Media Attachments
12. Virtex-6 FPGA 64B/66B Encoding and the Gearbox
Lab 7:GTX 64B/66B Encoding
13. Transceiver Board Design
14. Transceiver Test and Debugging
15. RocketIO Transceiver Test and Debugging
Lab 8:System Lab or IBERT Lab Using Xilinx Boards
16. Transceiver Application Examples
Lab Descriptions
Lab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency
differences on the TX and RX clocks.
Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.
Lab 5: GTP Core Generation – Use the GTP Wizard to create instantiation templates.
Lab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design.
Lab 7: GTX 64B/66B Encoding – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results
Lab 8: System Lab – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.
