HARDWARE

Designing for Performance

Nº 532
DATE: CALL Other available dates:
PRICE NIS: 2520 + VAT /6 Tcs
DURATION: 2 Days

Course Overview:

Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.
This course focuses on the Spartan-6 and Virtex-6 architectures.

Level:

FPGA3

Who should attend?

FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools.

Prerequisities:

Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
Intermediate HDL knowledge (VHDL or Verilog)
Solid digital design background

Skills Gained:

After completing this training, you will be able to:

Describe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAs
Create and integrate cores into your design flow by using the CORE Generator™ software system
Describe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performance
Increase performance by duplicating registers and pipelining
Increase system reliability by adding an appropriate synchronization circuit
Describe different synthesis options and how they can improve performance
Describe a flow for obtaining timing closure
Pinpoint design bottlenecks by using Timing Analyzer reports
Apply advanced timing constraints to meet your performance goals
Use advanced implementation options to increase design performance

Software Tools:

ISE Design Suite: Logic or System Edition 13.1

Hardware

Architecture: Spartan®-6 FPGA
Demo board: Spartan-6 FPGA SP605 board

Course Outline:

1. Review of Essentials of FPGA Design

2. Designing with FPGA Resources

3. CORE Generator Software System

4. Basic FPGA Clock Resources

5. Virtex-6 and Spartan-6 FPGA Clock Resources
Lab 1:Designing With FPGA Resources

6. FPGA Design Techniques

7. Synthesis Techniques
Lab 2:Synthesis Techniques

8. Achieving Timing Closure
Lab 3:Review of Global Timing Constraints

9. Path-Specific Timing Constraints, Part 1

10. Path-Specific Timing Constraints, Part 2
Lab 4:Achieving Timing Closure

11. Advanced Implementation Options
Lab 5:Designing for Performance
Lab 6:FPGA Editor Demo (optional)

12. ChipScope Pro Software (optional)
Lab 7:ChipScope Pro Software (optional)

Lab Descriptions

Lab 1: Designing with FPGA Resources– Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.

Lab 2: Synthesis Techniques– Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results.

Lab 3: Review of Global Timing Constraints– Use the Constraints Editor to enter global timing constraints.

Lab 4: Achieving Timing Closure– Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.

Lab 5: Designing for Performance– Improve performance and maximize results solely with implementation options and SmartXplorer.

Lab 6: FPGA Editor Demo (optional)– Use the FPGA Editor to view a design and add a probe to an internal net.

Lab 7: ChipScope Pro Software (optional)– Add an internal logic analyzer to a design to perform real-time debugging.

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