HARDWARE

Interested in learning how to utilize Virtex™-5 FPGA architectural resources effectively? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device. Topics covered include a Virtex-5 FPGA overview, new CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources.
Additionally, the new resources available in the LXT platform (EMAC, PCI Express, and GTP) are discussed. A combination of modules and labs allow for practical hands-on application of the principles taught.

Level:

Intermediate

For those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. A comprehensive knowledge of the Virtex-4 family architecture is also required. This material should be considered a Virtex-5 FPGA update course from the Virtex-4 FPGA family.

• Fundamentals of FPGA Design course
• Designing for Performance course
• Designing with the Virtex-4 Family course
• Comprehensive knowledge of the Virtex-4 FPGA

 

Software Tools:

• Xilinx ISE
• Synplicity Synplify Pro
• Mentor Graphics Precision

Skills Gained

After completing this training, you will be able to:

• Describe the 6-input LUT of the Virtex-5 FPGA
• Specify the CLB arrangement in the Virtex-5 FPGA
• Define the block RAM resources of the Virtex-5 FPGA
• Differentiate the arithmetic logic resources of the DSP48E slice in the Virtex-5 FPGA
• Identify the clocking resources of the Virtex-5 FPGA
• Describe the new PCI Express hard core
• Describe the new GTP transceiver
• Describe the new TEMAC hard core
• Describe the System Monitor