HARDWARE

VLSI-DSP for the ASIC and FPGA Engineer

Nº 641
DATE: CALL
PRICE NIS: 3780 + VAT
DURATION: 3 Days

VLSI-DSP for the ASIC and FPGA Engineer.pdf

Course Overview:

Many applications in today's technological world require fast DSP processing. Anything from physical layer processing in communication infrastructure to extraordinary image and sound processing in medical equipment. DSP is a unique area in VLSI design. There are many ways to implement the same DSP algorithm, though the efficient implementation may not be so obvious and would usually require particular expertise.The course introduces important basic concepts in DSP designing, surveys a variety of structures and advanced DSP implementations in VLSI.
The course is largely based on examples and relevant hands-on analytical exercises.

Level:

Intermediate

Who should attend?

Hardware design engineers (ASIC/FPGA)

Prerequisities:

Thorough knowledge in digital circuits design
Basic knowledge in digital signal processing

Course Outline:

1. Introduction

What is DSP?
Sampling Theory (Nyquist)
- Nyquist
- Sampling rate
- Bit width
DSP building blocks
Representing a DSP algorithm

2. Basic Arithmetic

Number systems and representations
- Floating point
- Fixed point
- Signed/unsigned
- Representing fractions
Arithmetic operations
- Addition
- Addition trees and chains accumulation
- Multiplication
Fixed point operations
- Quantization
- Overflow

3. Basic Filters

Convolution and correlation
IIR
- Direct form I and II
- Transposed form
- Quantization & overflow
FIR
- Direct form I and II
- Transposed form
- GLP
- Symmetry
- Throughput & processing rate
- MAC
- Adaptive filters
Multirate
- Up sampling
- Down sampling
- Interpolation
- Decimation
- Polyphase
- Half band
- Multi stage
- Filter banks
- Multi channel processing
- Block processing

4. Scaling and Roundoff Noise

State-variable description
Noise computation
- Scaling
- Roundoff

5. Advanced Arithmetic

Bit-level arithmetic
- Multiplication (carry ripple, carry save,
- baugh-wooley, booth, CSD, Horner)
- Distributed arithmetic
Numerical strength reduction
- Subexpression elimination
- MCM
- Subexpression sharing
- CSD common subexpressions

6. Advanced Filtering

Pipelining and parallel in FIR
Retiming
- Cutsets (FIR)
- Systematic retiming for systems with cycles (period and register minimizations)
Folding
- Register minimization (lifetime analysis)

Fast convolution
- Cook Toom
Fast FIR algorithms
- Polyphase
Pipelining IIR

7. Applications (optional)

Matrix transpose
- Using memories
- NCO
Dithering, Taylor correction
CVI
- Chebychef polynomials
- Farrow structure
FFT
- DIT, DIF, fixed point issues

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