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HARDWARE

Essentials of Microprocessors

Nº 566
DATE: CALL
PRICE NIS: 2520 + VAT /6 Tcs
DURATION: 2 Days
application/pdf iconEssentials of Microprocessors.pdf

Course Overview:
Learn what makes microprocessors tick! This class offers insights into all major aspects of microprocessors, from registers through coprocessors and everything in between. Differences between RISC and CISC architectures are explored as well as the concept of interrupts. A generic microprocessor is programmed and run in simulation to reinforce the principles learned in the lecture modules. The student will leave the class well prepared for the Xilinx Zynq training curriculum.

Level:
Embedded 1

Who should attend?
Novices to microprocessors or those who just need a refresher on microprocessor architecture

Prerequisities:
None

Software Tools:
Microprocessor simulator provided with the lab materials

Skills Gained:
After completing this training, you will be able to:
  • Describe the key components of a generic microprocessor
  • List common peripherals used with a microprocessor
  • Write a simple assembly language program
  • Describe the process of converting assembly language program into usable code

Course Outline:

1. Overview of a Generic Microprocessor

2. Exercise 1 – Generic Microprocessor Block Diagram

3. Generic Assembly Language

4. Exercise 2 – Playing Computer
Lab 1: Programming the Generic Microprocessor

5. Generic Interrupts
Lab 2: Write an Interrupt-Driven Program

6. Interfacing with Memory

7. Advanced Microprocessor Features

8. Processor Architecture Comparison
 


Lab Descriptions

Lab 1: Programming the Generic Microprocessor - Explore how to control a basic microprocessor and move data to and from memory by using assembly language.

Lab 2: Write an Interrupt-Driven Program – Examine the benefits of coding by using interrupts to detect external activities. Special interrupt instructions are covered, including enabling and disabling interrupts, writing interrupt handlers, and how the stack and registers are affected during an interrupt.

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