HARDWARE
Designing with the PlanAhead tool
Nº
535
DATE: 29-31.05.12
PRICE NIS: 3780 + VAT /9 Tcs
DURATION: 3 Days
DATE: 29-31.05.12
PRICE NIS: 3780 + VAT /9 Tcs
DURATION: 3 Days
Course Overview:
Learn to increase design performance and achieve repeatable results, plan an I/O pin layout, and implement by using the PlanAhead software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool, synthesis and project tips, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope Pro tool, and design preservation with partitions.
Level:
Intermediate
Who should attend?
FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.
Prerequisities:
Essentials of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE software flow.Designing for Performance recommended.
After completing this training, you will be able to:
Software Tools:
ISE Design Suite: Logic System Edition 13.1
Skills Gained:
After completing this training, you will be able to:- Use the most advanced features of the PlanAhead software
- Use the PlanAhead software integrated with the ISE Project Navigator software environment
- Assign I/O pins for optimum speed
- Run the Design Rule Checker (DRC) and perform noise analysis
- Import HDL sources and elaborate and analyze RTL netlists
- Implement the design with different implementation strategies
- Instantiate a core from the Xilinx IP Catalog
- Take advantage of the ISim simulator
- Apply the hierarchical viewer and timing report information to make the best area constraints
- Group the best logic into Pblocks
- Import HDL sources, elaborate, and analyze an RTL netlist
- Implement the design with different implementation strategies
- Analyze design statistics, connectivity, timing, placement, and timing critical paths
- Insert ChipScope Pro tool debug cores
- Floorplan the design to improve performance and preserve successful implementation results
- Make placement constraints for dedicated hardware resources
Course Outline:
1. PlanAhead Software Benefits and Features Overview
2. PlanAhead Software Project Manager
Lab 1: Getting Started with the PlanAhead Software
3. I/O Pin Planning
Lab 2: Assigning I/O Pins
4. CORE Generator Software Integration
Lab 3: Core Integration
5. Static Timing Analysis with the PlanAhead Software
6. Project Navigator Integration
7. PlanAhead Software Review
Lab 4: PlanAhead Software Review
8. RTL Development and Analysis
Lab 5: RTL Analysis
9. Placing Dedicated Resources
Lab 6: Placing Dedicated Resources
10. Introduction to Pblocks
11. Floorplanning Techniques
12. Floorplanning Case Studies
Lab 7: Design Analysis and Floorplanning for Performance
13. Design Preservation with Partitions
Lab 8: Leveraging Design Preservation for Predictable Results
14. Debugging with the ChipScope Pro Tool
Lab 9: Debugging with the ChipScope Tool
15. Tcl Scripting in the PlanAhead Software
Lab 10: Tcl Ccommands
16. (Optional): Team Design
17. (Optional): Routing Optimization in Virtex-6 Devices
18. Course Summary
2. PlanAhead Software Project Manager
Lab 1: Getting Started with the PlanAhead Software
3. I/O Pin Planning
Lab 2: Assigning I/O Pins
4. CORE Generator Software Integration
Lab 3: Core Integration
5. Static Timing Analysis with the PlanAhead Software
6. Project Navigator Integration
7. PlanAhead Software Review
Lab 4: PlanAhead Software Review
8. RTL Development and Analysis
Lab 5: RTL Analysis
9. Placing Dedicated Resources
Lab 6: Placing Dedicated Resources
10. Introduction to Pblocks
11. Floorplanning Techniques
12. Floorplanning Case Studies
Lab 7: Design Analysis and Floorplanning for Performance
13. Design Preservation with Partitions
Lab 8: Leveraging Design Preservation for Predictable Results
14. Debugging with the ChipScope Pro Tool
Lab 9: Debugging with the ChipScope Tool
15. Tcl Scripting in the PlanAhead Software
Lab 10: Tcl Ccommands
16. (Optional): Team Design
17. (Optional): Routing Optimization in Virtex-6 Devices
18. Course Summary
Labs Descriptions
Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead software so that you can synthesize, implement, perform timing analysis, view logical and device resources, and generate a bitstream. Also introduces the PlanAhead software's environment and views.
Lab 2: Assigning I/O Pins – Introduces the PlanAhead software’s pin planning environment for performing I/O pin assignment. You will create a pin planning project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, examine clock logic placement, and make pin assignments.
Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator software with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.
Lab 4: PlanAhead Software Review – Illustrates the steps you take to import source HDL files into the PlanAhead tool and synthesize, implement, and analyze the results. Also introduces the PlanAhead tool environment and views.
Lab 5: RTL Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).
