HARDWARE
Designing with the TMR Tool
Nº
536
DATE: CALL
PRICE NIS: 2520 + VAT
DURATION: 2 Days
DATE: CALL
PRICE NIS: 2520 + VAT
DURATION: 2 Days
Course Overview:
The TMR Solution for Next-Generation Space Applications
New approaches have been developed to address Single-Event Upsets (SEUs) and Single-Event Transients (SETs) in re-programmable logic devices including Virtex™, Virtex-II, Virtex-II Pro and Virtex-4. The XTMR methodology along with scrubbing provides full SEU and SET immunity for any high reliability Virtex FPGA.
This course provides a solid working knowledge of the Xilinx TMRTool and the XTMR design flow. This course also offers background and insight on the historic SEU, SET, and SEFI challenges that designers face when deploying any electronic circuitry in space. The focus of the course is the unique challenges that user-programmable FPGAs present and how TMRTool greatly simplifies the TMR process for a Xilinx FPGA. Throughout the course, you will explore the key features and capabilities of the TMRTool and understand possible TMR tradeoffs.
New approaches have been developed to address Single-Event Upsets (SEUs) and Single-Event Transients (SETs) in re-programmable logic devices including Virtex™, Virtex-II, Virtex-II Pro and Virtex-4. The XTMR methodology along with scrubbing provides full SEU and SET immunity for any high reliability Virtex FPGA.
This course provides a solid working knowledge of the Xilinx TMRTool and the XTMR design flow. This course also offers background and insight on the historic SEU, SET, and SEFI challenges that designers face when deploying any electronic circuitry in space. The focus of the course is the unique challenges that user-programmable FPGAs present and how TMRTool greatly simplifies the TMR process for a Xilinx FPGA. Throughout the course, you will explore the key features and capabilities of the TMRTool and understand possible TMR tradeoffs.
Level:
Fundamental to Intermediate
Who should attend?
Any design engineer who creates hardware with TMR requirements. This includes spaced-based deployment or similarly hostile environments.
Prerequisities:
- Basic digital design knowledge
Software Tools:
- TMRTool
- ISE
- ModelSim SE
- PlanAhead
Skills Gained:
After completing this training, you will be able to:
- Recognize and address unique FPGA TMR challenges
- Perform comprehensive TMR for Xilinx FPGAs
- Prioritize SEU/SET risks against area and pinout limitations
- Incorporate device scrubbing into TMR strategy
- Create effective timing constraints for TMR design
- Modify testbenches to handle post-TMR circuits
- Incorporate TMRTool into the standard ISE design flow
- Choose the best overall solution for maximum SEU/SET immunity
Course Outline:
1. Xilinx FPGA Radiation Effects Summary
- Virtex-II Radiation Effects Summary
- Configuration Memory Cells
- User Memory
- SEFI and SET Effects
- Summary
2. Mitigation Selection Scheme
- Application Requirement
- Mitigation Schemes Selection
3. XTMR and Scrubbing Overview
- Classic TMR Solutions
- XTMR (Xilinx Triple Module Redundancy)
- Device Scrubbing
- Summary
4. Virtex-II Configuration Architecture and Mitigation
- Configuration Overview
- Configuration Architecture and Registers
- Configuration Management Operations
- SEFIs
- Configuration Management IP Development
5. Virtex-4 Configuration Architecture and Mitigation
- Configuration Overview
- Configuration Architecture and Registers
- Configuration Management Operations
- SEFIs
- Configuration Management IP Development
- Introduction
- Lab
- Review
- Half-Latch Removal
- XTMR Types
- Output Types
- Summary
- Introduction
- Global Constraints
- The Constraints Editor
- XTMR Timing Constraints
- Summary
- Introduction
- Lab
- Review
8. Performance and Application Issues
- Clock Alignment Issues
- Signal Integrity Issues
- The Cost of Half-Latch Removal
- Partial XTMR
- FAQs
- Summary
Lab 3: Application Lab
- Introduction
- Lab
- Review
9. Additional Design Considerations
- Output Selection
- Memory Elements
- FSM
- DCM
- Others
- Verification
Lab 4: Bram Scrubber
- Introduction
- Lab
- Review
Lab Descriptions
This course is a lab-intensive, one-day workshop that gives you practical hands-on experience with TMRTool, design verification, timing constraints, and device implementation.
Each lab exercise offers insight to the underlying concepts, while enhancing designer skills and productivity. The exercises are briefly described here.
Lab 1 - Basic TMRTool Flow:Incorporate the TMRTool into the overall ISE design flow, set XTMR options, and export the post-TMR design.
Lab 2 - Timing Constraints and Design Verification:Update timing constraints for TMR designs, modify the testbench for post-TMR design verification.
Lab 3 - Performance and Application Issues: Evaluate trade-offs for output registers and bidirectional I/O, and assess impact of half-latch removal.
Lab 4 - BRAM Scrubber: Putting It All Together
