HARDWARE
FPGA Architecture and ISE Features
Nº
537
DATE: CALL
PRICE NIS: 2520 + VAT /6 Tcs
DURATION: 2 Days
DATE: CALL
PRICE NIS: 2520 + VAT /6 Tcs
DURATION: 2 Days
Course Overview:
ISE Design Tool Flow provides the overall context and framework for the development cycle of FPGAs. For those uninitiated to FPGA design, this course will arm you with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design now.
The flow will take you from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced.
Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.
The flow will take you from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced.
Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.
Who should attend?
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the ISE 13.1 design tools
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
Prerequisities:
Working HDL knowledge (VHDL or Verilog)
Digital design experience
Software Tools:
ISE 13.1
Hardware
Architecture: Spartan®-6 FPGA
Demo board: Spartan-6 FPGA SP605 board
Skills Gained:
After completing this training, you will be able to:
• Outline a complete project planning process
• Create a new Project Navigator project in the ISE software
• Access and modify Xilinx Synthesis Technology (XST) synthesis options
• Assign pin locations using the I/O Planner
• Enter global clock constraints using the Xilinx Constraints Editor
• Simulate a design using the ISim Simulator
• Take advantage of the primary features of the Spartan-6 FPGA
• Use the Xilinx Project Navigator to implement and simulate an FPGA design
• Read reports and determine whether your design goals were met
• Use the Clocking Wizard to create DCM instantiations
• Use the I/O Planner to make good pin assignments
• Use the Xilinx Constraints Editor to enter global timing constraints
Course Outline:
1. Course Agenda
2. Project Planning
3. Basic FPGA Architecture
4. Projects in the Project Navigator
5. Xilinx Tool Flow
Lab 1:Projects in the Project Navigator
6. HDL Synthesis and XST
Lab 2:XST Synthesis Options
7. Constraints and the I/O Planner
Lab 3:Pre-Assigning I/O Pins Using the PlanAhead Tool
8. Global Timing Constraints
Lab 4:ISim Simulator
9. Additional Features
Lab 5:Xilinx Tool Flow
10. Reading Reports
Lab 6:Clocking Wizard and Pin Assignment
Lab 7:Global Timing Constraints
11. Synchronous Design Techniques
12. Course Summary
Labs Description
Lab 1: Projects in the Project Navigator – Gain comprehensive hands-on experience with the HDL flow in the ISE software. Create a new project, add source files, synthesize a design, and use the error navigation feature to fix your HDL code.
Lab 2: Synthesis Options – Modify XST synthesis properties, read synthesis reports to compare the synthesis results with the implemented results, and use the schematic viewer to evaluate the design.
Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.
Lab 4: ISim Simulator – Use the project navigator to view an HDL testbench, use the ISim Simulator to run simulation view output waveforms, add signals, and change their viewed format.
Lab 5: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.
Lab 7:Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint
