HARDWARE

Designing with Verilog

Nº 521
DATE: 24-27.06.12
PRICE NIS: 5040 + VAT /12 Tcs
DURATION: 4 Days

Course Overview:

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Level:

FPGA1

Who should attend?

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Prerequisities:

Basic digital design knowledge

Software Tools:

ISE Design Suite: Logic or System Edition 13.1

Hardware:

Demo board: Spartan-6 FPGA SP605 board

Skills Gained:

After completing this training, you will be able to:

Write RTL Verilog code for synthesis
Write Verilog test fixtures for simulation
Create a Finite State Machine (FSM) by using Verilog
Target and optimize Xilinx FPGAs by using Verilog Use enhanced Verilog file I/O capability
Run a timing simulation by using Xilinx Simprim libraries
Create and manage designs within the ISE software design environment
Download to the Spartan-6 FPGA SP605 demo board

Course Outline:

1. Hardware Modeling Overview

2. Verilog Language Concepts

3. Modules and Ports
Lab 1:Building Hierarchy

4. Introduction to Testbenches
Lab 2:Verilog Simulation and RTL Verification

5. Verilog Operators and Expressions

6. Data Flow-Level Modeling
Lab 3:Memory

7. Verilog Procedural Statements
Lab 4:Clock Divider and Address CounterControlled Operation Statements
Lab 5:n-bit Binary Counter and RTL Verification

8. Verilog Tasks and Functions

9. Advanced Language Concepts
Lab 6:Timing Simulation

10. Finite State Machines
Lab 7:Finite State Machines

11. Targeting Xilinx FPGAs
Lab 8:Implement and Download

12. Advanced Verilog Testbenches
Lab 9:Using Verilog File I/O

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation

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