HARDWARE

SystemVerilog for Design and Verification

Nº 525
DATE: CALL
PRICE NIS: 5040 + VAT
DURATION: 4 Days

Course Overview:

This comprehensive 4-days hands-on intensive course provides complete and integrated training program. It provides the participants with a deep knowledge of 1800-2005 SystemVerilog. The goal of this course is to fulfill the needs and requirements of engineers wanting to exploit the breadth of SystemVerilog features for both design and verification.

Level:

Intermediate to Advanced

Who should attend?

Experienced Verilog design and verification engineers wanting to use System Verilog 1800-2005 features for modeling, synthesis and verification of digital designs

Prerequisities:

Digital design knowledge, Verilog 1364-1995 and Verilog 1364-2001

Skills Gained:

After completing this training, you will be able to:
Use System Verilog design advanced techniques Create libraries and configurations Build abstract models for verification of digital designs, using class-based object oriented constructs Create random, coverage driven simulation environment

Course Outline:

1. Verilog short history brief

2. SystemVerilog data types

3. User-defined types, structs and unions

4. Procedural statements and flow control

5. Arrays and lists

6. Interfaces and Clocking Blocks

7. SystemVerilog new operators

8. Packages and configuration libraries

9. Programs and module binding

10. Transaction Level Modeling (TLM)

11. Object oriented modeling - structs and classes

12. Random and constrained simulation

13. Direct Programming Interface (DPI)

14. Assertions

15. Coverage

Topics brakdown

Verilog Evolution
Data Types
Strings
Enumerated Data Types
User-defined types
Structs and Unions
Arrays

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