HARDWARE

Active-HDL 8.2 Trainings

Nº 802
DATE: CALL
PRICE NIS: 2520 + VAT
DURATION: 3 Days

Course Overview:

Active-HDL is an integrated easy-to-use FPGA Design and Simulation solution, providing a robust design creation tool suite, a high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for industry leading FPGA devices, such as Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and over 87 popular EDA tools, all-in-one common environment.
The Active-HDL 8.2 Training will provide you with the know-how for best practice of Active-HDL via hands-on experience.

Prerequisities:

None

Course Outline:

1. Design Entry & Management

Creating HDL Text Modules– Learn how to create HDL Text Modules in using Active-HDL
Creating HDL Graphical Modules– Learn how to create HDL Graphical Modules using Active-HDL
Design Management– Learn about Design Management using Active-HDL’s complete set of management tools

2. Design Verification

HDL Debugging– Learn how to use the debugging tools in Active-HDL
Running Simulation– How to setup and run simulations using Active-HDL
Creating Testbenches– Learn how to create testbenches using Active-HDL
Code and Toggle Coverage– Learn to use the Code Coverage tools in Active-HDL
Design Profiler– Learn to use the integrated Design Profiler tool is Active-HDL

3. Active-HDL Interfaces

Building VHPI Applications C Compilation- Building VHPI Applications C Compilation in Active-HDL
Debugging C Code- Debugging C Code in Active-HDL

4. Interfaces to External EDA Tools -Learn to useActive-HDL's various interfaces to external EDA Tool:

Debussy
Denali
SWIFT™

5. Active-HDL Interfaces

Simulink® Interface - Learn to use the Active-HDL Simulink® Interface. Active-HDL provides an interface to MATLAB and Simulink simulation environment, which allows co-simulation of functional blocks described by using mathematical formulas and behavioral models described by using hardware description languages

6. Native SystemC Support in Active-HDL

Design Entry and Simulation- Learn about Active-HDL's Native SystemC Support capabilities

7. Accelerated Waveform Design Entry and Simulation

Learn about the Accelerated Waveform Viewer and its functionality in Active-HDL

8. Documentation Features -Learn about the Active-HDL Documentation Features

HDL Design & Verification LAB
This is an interactive HDL Design & Verification LAB for Active-HDL users

Creating a Behavioral Design
Creating CNT_BCD module
Simulating with the waveforms
Debugging Features
Using Testbench Wizard
Creating top level Block Diagram
Creating State Diagrams
Simulating Top-Level

Appendices

Synthesis & Implementation
Using Code Coverage
Importing Foundation Designs
Using Verilog PLI
WAVES Testbenches
How to create a Diagram from HDL
State Diagram
State Diagram Junction & Auto Priority
VHPI Interface

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