HARDWARE

How to Design a High-Speed Memory Interface

Nº 557
DATE: 06-07.06.12
PRICE NIS: 2520 + VAT
DURATION: 2 Days

How to Design a High-Speed Memory Interface.pdf

Course Overview:

This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using Spartan®-6 and Virtex®-6 FPGAs. Additionally, you will learn about the tools available for high-speed memory interface design, implementation, and debugging.

Level:

Connectivity 3

Who should attend?

FPGA designers and logic designers

Prerequisities:

VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
Familiarity with logic design: state machines and synchronous design
Very helpful to have:
- Basic knowledge of FPGA architecture
- Familiarity with Xilinx implementation tools

Nice to have:
- Familiarity with I/O basics
- Familiarity with high-speed I/O standard

Software Tools:

ISE Design Suite 13.1
Mentor Graphics HyperLynx 8.0 or later

Skils Gaind:

After completing this trainind, you will be able to:

Identify the FPGA resources required for memory interfaces
Describe different types of memories
Utilize the Xilinx tools to generate memory interface designs
Simulate memory interfaces with the Xilinx ISim simulator
Implement memory interfaces
Identify the board design options for the realization of memory interfaces
Describe PCB-level simulation
Test and debug your memory interface design

Course Outline:

1. Introduction

2. Spartan-6 and Virtex-6 Family Overview

3. Memory Devices

4. Spartan-6 FPGA Memory Interfaces

5. Virtex-6 FPGA Memory Interfaces

6. MIG Design Generation
Lab 1: MIG Core Generation

7. MIG Design Simulation
Lab 2: MIG Design Simulation

8. MIG Design Implementation
Lab 3: MIG Design Implementation

9. Memory Interface Board-Level Design

10. Memory Interface PCB Simulation
Lab 4: DDR3Signal Integrity Simulation

11. Memory Interface Test and Debugging
Lab 5:MIG Design Debugging

Lab Descriptions

Lab 1: MIG Core Generation – Create a DDR2 or DDR3 memory controller using the Memory Interface Generator (MIG) CORE Generator™ interface. For Spartan-6 devices, customize the hard Memory Controller Block (MCB) targeting the SP601 or SP605 board. For Virtex-6 devices, customize the soft core memory controller for the ML605 board.

Lab 2: MIG Design Simulation – Simulate the memory controller created in Lab 1 using ISim.

Lab 3: MIG Design Implementation – Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.

Lab 4: Signal Integrity Simulation – Evaluate and perform basic verification options available for IBIS simulation of memory interfaces.

Lab 5: MIG Design Debugging – Debug the memory interface design utilizing the ChipScope Pro™ tool.

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