HARDWARE
Signal Integrity and Board Design Using HyperLynx
Nº
553
DATE: CALL Other available dates:
PRICE NIS: 5040 + VAT
DURATION: 3 Days
DATE: CALL Other available dates:
PRICE NIS: 5040 + VAT
DURATION: 3 Days
Course Overview:
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
Connectivity 3
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
Level:
Connectivity 3Who should attend?
Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.
Prerequisities:
- FPGA design experience preferred (Essentials of FPGA Design course or equivalent)
- Familiarity with high-speed PCB concepts
- Basic knowledge of digital and analog circuit design
- ISE® tool knowledge is helpful
Software Tools:
ISE Design Suite 13.1Mentor Graphics HyperLynx 8.0 or later
Skills Gained:
After completing this training, you will be able to:
- Describe signal integrity effects
- Predict and overcome signal integrity challenges
- Simulate signal integrity effects
- Verify and derive design rules for the board design
- Apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and semiconductor circuits
- Plan your board design under FPGA-specific restrictions
- Supply the FPGAs with power
- Handle thermal aspects
Course Outline:
Part 1 – Signal Integrity
1. Signal Integrity Introduction
- What is High Speed Board Design
- Digital Vs. Analog world
- Various effects on electrical signal
2. Transmission Lines
- Theory Basic transmission line
- Critical Trace Length in the Time Domain
- Critical Trace Length in the Frequency Domain
- Propagation Delay Time on Layers: External & Internal
- PCB Conductors
- Distributed T-Line Representation
- Low Frequency versus High Frequency Return Path
- Lossy Lines vs. Lossless Lines
- Skin Effect, Skin depth calculation
- 10G Traces
3. IBIS Models and SI Tools
- What are IBIS Files?
- IBIS Editor, Steps to Create An IBIS Model
- Reading IBIS Files
- Reviewing SI tools
- Lab 1:Invoking HyperLynx
4. Reflections
- Reflection Effects
- Reflection Calculations, Value of Series Resistor
- Trace Termination
- Reflection on Different Topologies: Start, Daisy Chain,
- Lab 2:Reflection Analysis
5. Crosstalk
- Crosstalk in transmission line
- Capacitive XTalk, Inductive XTalk
- Crosstalk calculation
- XTalk and PCB Layer Stackup
- Technique for Minimizing XTalk
- Lab 3: Crosstalk Analysis
6. Signal Integrity Analysis
- Methods for SI Analysis
- Package Modeling
- Via Modeling
- System Analysis
- Serial Transceiver SI Design Kits
- Memory Interface Analysis – DDR3/2
7. Power Supply Issues
- Impedance and Inductance of the Power Supply
- Bypass Capacitors – Calculate Bypass Capacitor
- Power Supply on Board Level – Critical Location
- Tool Support - HyperLynx
8. Signal Integrity Summary
Part 2 – Board Design
9. Board Design Introduction
10. FPGA Power Supply
- Power Supply Design Flow
- Power Supply Estimation
- Supply Voltage Generation, General schemes , available solutions
- Power Distribution and Bypassing
- Calculating a Power Supply Filter
- Simulation Tools
- Lab 4: Power Prediction
11. FPGA Configuration and PCB
- Configuration Interfaces
- Configuration Memory
- Configuration Applications
- Board Design Issues
12. Signal Interfacing: Interfacing in General
- Combining High-Speed I/O Standards - Equal Standards, Different Standards
- High-Speed Clocks on PCB
- Designing with LVPECL and LVDS
- On-Chip Termination - Split
- Serial I/O (Data and Clock Pins)
- Simultaneous Switching Outputs
- Lab 5: I/O Pin Planning
13. Die Architecture and Packaging
- Die and Package Relationship
- Pin Placement Considerations
14. PCB Details
- PCB Technology
- PCB Traces
- Trace & Via Characteristics
- Layer Stackup and Rules
- FPGA Packages and Routability
15. Thermal Aspects
- Basic principal of Heat Flow
- Thermal Resistance Calculation
- Heat Sink Selection rules
- Lab 6: Thermal Design
16. Signal Integrity & Board design checklist
17. Board Design Summary
Lab Descriptions
Lab 1: Invoking HyperLynx– Become familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stackup editor to define a PCB.
Lab 2: Reflection Analysis– Define a circuit and run various simulations for effects of reflection.
Lab 3: Crosstalk Analysis– Using simulation, analyze circuit topology and PCB data for strategies to minimize crosstalk.
Lab 4: Power Prediction– Estimate initial power requirements using an Excel spreadsheet, then use XPower Analyzer to accurately predict board power needs.
Lab 5: I/O Pin Planning– Use the PlanAhead software to identify pin placement and implement pin assignments.
Lab 6: Thermal Design– Determine maximum junction temperature and calculate acceptable thermal resistance.
