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Hardware design has revolutionized the way the world interacts. Device capabilities continue to sky rocket today and designers must explore more ways to improve time to market. Debugging problems costs time and threatens stellar performance. Trial and error can push time to market to infinity and beyond.
Training fills the spaces between inefficiency and productivity. With Logtel high tech training, your engineers will find all the knowledge and skills necessary to go ahead and design the future. Advanced courses help you push the outer limits of the latest technologies. Logtel is also the Authorised Training Provider (ATP) in Israel and Turkey training Xilinx customers and partners.
Browse our variety of topics below. Logtel can also tailor-develop a training plan that fits your organization's current needs for the diverse background of your engineers. In-House sessions are offered to our clients on-site so you maintain your employee productivity throughout the training program. 'Public' training programs allow your selected employees starting from a single individual - to join training programs taking place at a Logtel training center.
* For more training opportunities, please check our Catalog or contact us for details.
| Course name | Coming Date | Duration (days) | More info | |||
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| FPGA TOOLS | ||||||
| Debugging Techniques using the ChipScope Pro tools | Call | 2 |
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As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug.
This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.
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| Designing FPGAs Using the Vivado Design Suite 1 | Call | 2 |
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This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow.
For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered. LevelFPGA 1[Close] |
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| Designing FPGAs Using the Vivado Design Suite 2 | Call | 3 |
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This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.
Level:FPGA 2[Close] |
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| Designing with the PlanAhead tool | Call | 3 |
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Learn to increase design performance and achieve repeatable results, plan an I/O pin layout, and implement by using the PlanAhead software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool, synthesis and project tips, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope Pro tool, and design preservation with partitions.
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| FPGA - Architecture and ISE Features | Call | 2 |
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ISE Design Tool Flow provides the overall context and framework for the development cycle of FPGAs. For those uninitiated to FPGA design, this course will arm you with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design now.
The flow will take you from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced. Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow. This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. [Close] |
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