Hardware Training

Hardware design has revolutionized the way the world interacts. Device capabilities continue to sky rocket today and designers must explore more ways to improve time to market. Debugging problems costs time and threatens stellar performance. Trial and error can push time to market to infinity and beyond.

Training fills the spaces between inefficiency and productivity. With Logtel high tech training, your engineers will find all the knowledge and skills necessary to go ahead and design the future. Advanced courses help you push the outer limits of the latest technologies. Logtel is also the Authorised Training Provider (ATP) in Israel and Turkey training Xilinx customers and partners.

Browse our variety of topics below. Logtel can also tailor-develop a training plan that fits your organization's current needs for the diverse background of your engineers. In-House sessions are offered to our clients on-site so you maintain your employee productivity throughout the training program. 'Public' training programs allow your selected employees starting from a single individual - to join training programs taking place at a Logtel training center.

* For more training opportunities, please check our Catalog or contact us for details.

Course name	Coming Date	Duration (days)	More info
HARDWARE DEFINITION LANGUAGES
Advanced Design with Verilog	Call	2	Click here This comprehensive 2 days course provides complete and integrated training program. It is structured as a comparison between traditional Verilog 1995 and newer Verilog standards – 1364-2001 and 1800-2005 System Verilog. The goal of this course is to fulfill needs and requirements engineers, who want to exploit wide breadth of System Verilog features for both design and basic testbench. Level: Intermediate to Advanced [Close] readMore Register
Designing with Verilog	12/05/19	4	Click here This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. Level: FPGA 1 [Close] readMore Register
Essential Tcl Scripting for the Vivado Design Suite	Call	1	Click here Learn how to use basic Tcl syntax and language structures to build scripts suitable for use with Xilinx FPGA design tools. Learn about the effective use of variables, data types, and Tcl constructs to build effective conditional statements and loop controls. You will also have the opportunity to use Tcl language constructs with several labs designed to provide you scripting experience within the Vivado™ Design Suite. Level: FPGA 1 [Close] readMore Register
Fast-track Verilog for VHDL Users	12/06/19	2	Click here Verilog for VHDL Users is an intensive 2-day course, converting knowledge of VHDL to practical Verilog skills. Contrasting Verilog and VHDL, this course demonstrates similarities and highlights differences between two hardware description languages and their associated design flows. The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools. Labs comprise about 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. [Close] readMore Register
SystemVerilog for Design and Verification	16/05/19	4	Click here This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs. This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. After completing this comprehensive training, you will have the necessary skills to: ▪ Describe the features and benefits of using SystemVerilog for RTL design ▪ Identify the new data types supported in SystemVerilog ▪ Use an enumerated data type for coding a finite state machine (FSM) ▪ Explain how to use structures, unions, and arrays ▪ Describe the new procedural blocks and analyze the affected synthesis results ▪ Define the enhancements and ability to reuse tasks, functions, and packages ▪ Identify how to simplify module definitions and instantiations using interfaces ▪ Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis ▪ Target and optimize Xilinx FPGAs by using SystemVerilog ▪ Synthesize and analyze SystemVerilog designs with the Vivado Design Suite ▪ Download a complete SystemVerilog design to an evaluation * This course does not focus on any particular architecture. Check with your local Authorized Training Provider for specifics or other customizations. After completing this comprehensive training, you will have the necessary skills to: ▪ Describe the advantages and enhancements to SystemVerilog to support verification ▪ Define the new data types available in SystemVerilog ▪ Analyze and use the improvements to tasks and functions ▪ Discuss and use the various new verification building blocks available in SystemVerilog ▪ Describe object-oriented programming and create a class-based verification environment ▪ Explain the various methods for creating random data ▪ Create and utilize random data for generating stimulus to a DUT ▪ Identify how SystemVerilog enhances functional coverage for simulation verification ▪ Utilize assertions to quickly identify correct behavior in simulation ▪ Identify how the direct programming interface can be used with C/C++ in a verification environment. Level: FPGA1 [Close] readMore Register
Verification with SystemVerilog	Call	2	Click here This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs. Level: FPGA 1 [Close] readMore Register
VHDL - Advanced	Call	2	Click here Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules. [Close] readMore Register
VHDL - Expert VHDL for Design and Verification	Call	3	Click here VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice. Expert VHDL is an intensive 6-days advanced application class. It teaches engineers how to increase productivity by enhancing their VHDL coding and application skills. Presented in two distinct course modules, Expert VHDL focuses on language and synthesis issues, design maintainability and re-use, test benches and the latest techniques for verification - including an introduction to OVL and modern assertion-based approaches to verification. Expert VHDL- Advanced Digital Design (3 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL, and to improve their VHDL coding style with design maintainability and re-use in mind. Design for Verification is also covered with an introduction to modern assertion-based techniques. Expert VHDL Verification (3 days) is for design engineers and verification engineers involved in VHDL test bench development or behavioral modeling for the purpose of functional verification. The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. [Close] readMore Register
VHDL - Xilinx Designing with VHDL	19/06/19	4	Click here This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. Level: FPGA 1 [Close] readMore Register
Xilinx SystemVerilog for Design and Verification	Call	4	Click here This comprehensive 4-days hands-on intensive course provides complete and integrated training program. It provides the participants with a deep knowledge of 1800-2005 SystemVerilog. The goal of this course is to fulfill the needs and requirements of engineers wanting to exploit the breadth of SystemVerilog features for both design and verification. Level: Intermediate to Advanced [Close] readMore Register

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Hardware Training

* For more training opportunities, please check our Catalog or contact us for details.

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