Hardware Training

Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express® core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.

Level:

Connectivity 3
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Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements. Become familiar with Ethernet IP core design architectures, core IP port naming conventions, and signal waveforms.
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In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.

Level:

Connectivity 3

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FPGA Introduction assuming VHDL is a known language.
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This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs.
Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.
The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR, and QDRII+. Labs are available for DDR3 on the Kintex™-7 FPGA KC705 board.

Level:

Connectivity 3

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Course Description
Are you interested in learning how to effectively utilize 7 series high-speed interface resources? This course supports both experienced and less experienced FPGA designers who have in minimum general digital hardware knowledge and basic information on 7 series FPGAs. Furthermore, first work with the new Xilinx VIVADO Design Suite is helpful.  This course focuses on understanding as well as how to properly design for the high-speed interface solutions found in the new device families: transceiver in general, PCI Express and memory interfacing complemented with board design issues. Topics covered include interface overviews, design usage, simulation, implementation and examples on real hardware.
This course also includes a detailed discussion about proper PCB design techniques that enables designers to avoid common mistakes and get the most out of their FPGA interfaces.
A combination of modules and labs allow for practical hands-on application of the principles taught.
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The course provides a detailed and comprehensive understanding of the PCI Express technology.
The course is fully up-to-date and supports the latest version of the international specification (3.0), and covers all aspects of the specification from a hardware design perspective and also discusses the software requirements of PCI Express implementations.
This course provides example implementations, and practical guidance that will give a running start on your design.
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This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.
Implementation issues are covered in the two-day Designing a LogiCORE PCI Express System course.

Level:

Connectivity 2
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Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.

Level:

Connectivity 3

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