Hardware Training

VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice. This training builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.

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Course description with information on the course – marketing oriented.
Open Verification Methodology (OVM) is a non-proprietary functional verification methodology based on SystemVerilog. The source code and documentation are freely available under an open-source Apache license. OVM offers a complete framework for the creation of sophisticated functional verification environments in SystemVerilog, and encourages the development and deployment of re-usable verification components.
It has comprehensive support for constrained random stimulus generation, including structured sequence generation, and for transaction-level modelling. OVM testbenches also support functional coverage collection and assertions. OVM exploits the object-oriented programming (or "class-based") features of SystemVerilog. The open structure, extensive automation, and standard transaction-level interfaces of OVM make it suitable for building functional verification environments ranging from simple block-level tests to the most complex coverage-driven testbenches.
Delegates for this course must start with a detailed knowledge of building class-based verification environments using SystemVerilog. The course leads delegates through to full verification project readiness by focussing on the in-depth practical application of OVM using commercial verification tools such as Mentor Graphics Questa™Sim and Synopsys® VCS®.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. During the hands-on workshops, delegates will build a complete OVM verification environment for a small example system.

Level: Standard Level OVM Training
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The Universal Verification Methodology (UVM) is a standard functional verification methodology for SystemVerilog, controlled by Accellera, and endorsed and supported by all major SystemVerilog simulator vendors. The source code and documentation are freely available under an open-source Apache license. UVM offers a complete framework for the creation of sophisticated functional verification environments in SystemVerilog, and encourages the development and deployment of re-usable verification components.
UVM has comprehensive support for constrained random stimulus generation, including structured sequence generation, and for transaction-level modeling. UVM testbenches also support functional coverage collection and assertions. UVM exploits the object-oriented programming (or "class-based") features of SystemVerilog. The open structure, extensive automation, and standard transaction-level interfaces of UVM make it suitable for building functional verification environments ranging from simple block-level tests to the most complex coverage-driven testbenches.
Delegates for this course must start with a detailed knowledge of building class-based verification environments using SystemVerilog. The course leads delegates through to full verification project readiness by focusing on the in-depth practical application of UVM using commercial verification tools such as Cadence Incisive® Enterprise Simulator, Mentor Graphics Questa™Sim, and Synopsys® VCS®.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. During the hands-on workshops, delegates will build a complete UVM verification environment for a small example system.
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SystemVerilog (IEEE 1800™) is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture.
SystemVerilog for Verification Specialists provides a 4 day training program to fulfil the requirements of verification engineers or those wishing to evaluate SystemVerilog's applicability for complex verification application. It is structured to enable engineers to develop their skills to utilise the full breadth of SystemVerilog features for verification. This includes how to exploit the potential of class-based verification and object oriented techniques using SystemVerilog, as well as application for standard test bench development and module-based verification.
The course assumes Verilog knowledge but no prior SystemVerilog knowledge. VHDL users preparing to use SystemVerilog should consider preparatory training with the 2 day Fast Track Verilog for VHDL Users.
The course includes an introduction to UVM (and OVM) but full scope project readiness in UVM requires follow-on training with the 3 day UVM Adopter Class.
Design engineers (FPGA or ASIC) who intend to use SystemVerilog for RTL design and basic test bench development should attend the companion training course SystemVerilog for FPGA/ASIC Design.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.
Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology.

Level: Standard Level
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VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
This trainingprepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.
Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. 

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