Advanced Design with Verilog
Start Date: 09/05/2023
Course Overview
This comprehensive 2 days course provides complete and integrated training program. It is structured as a comparison between traditional Verilog 1995 and newer Verilog standards – 1364-2001 and 1800-2005 System Verilog. The goal of this course is to fulfill needs and requirements engineers, who want to exploit wide breadth of System Verilog features for both design and basic testbench.
Level:
Intermediate to AdvancedWho should attend?
Experienced Verilog design and engineers who want to use Verilog 1364-2001 and SystemVerilog 1800-2005 features for modeling, synthesis and verification of digital designsPrerequisite:
Digital design knowledge, Verilog 1364-1995
Software Tools:
Modelsim – Mentor Graphics
Skills Gained: After completing this training, you will be able to:
After completing this training, you will be able to:
- Use Verilog 2001 and System Verilog design advanced techniques
- Create reusable parameterized designs and verification models
- Create libraries and configurations
- Build abstract models for verification of digital designs, using class-based object oriented constructs
Course Outline:
Verilog 2001
1. Parameters and local parameters enhancements
2. Functions and tasks
3. Arrays and Vectors
4. Generate statement
5. Signed Arithmetic
6. Data Types
7. New Operators
8. New pre-compiler directives
9. Attributes
10. Enhanced File IO
11. Standard SDF Support
12. Libraries and Configurations
System Verilog
13. Data Types
14. Enumerated Data Types
15. Arrays
16. New Operators
17. Unique and priority decision statements
18. Functions
19. Instances and Port Connection Enhancements
20. Clocking Blocks
21. Bind Operator
22. Packages
23. Assertions
