Start Date: 07/03/2022
Advanced Features and Techniques of Embedded Systems Design provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Vivado™ IP Integrator. This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system in the Zynq™ All Programmable System on a Chip (SoC) or Microblaze™ soft processor.
This course builds on the skills gained in the Embedded Systems Design course. Labs provide hands-on experience with developing, debugging, and simulating an embedded system. Utilizing memory resources and implementing high-performance DMA are also covered. Labs use demo boards in which designs are downloaded and verified.
Level:Embedded Hardware 4
Who should attend?Hardware, firmware and system design engineers who are interested in Xilinx embedded systems development flow.
• Embedded Systems Design course or experience with embedded systems design and the Vivado Design Suite
• Basic C programming
• Working knowledge of the Zynq All Programmable SoC or Microblaze processor
• Vivado Design or System Edition 2017.3
• Architecture: Zynq-7000 All Programmable SoC and 7 series FPGAs*
• Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*
Skills Gained: After completing this training, you will be able to:
• Assemble an advanced embedded system
• Take advantage of the various features of Zynq All Programmable SoC and Kintex™ FPGAs, Cortex™-A9 and Microblaze processors, including the AXI interconnect and various memory controllers
• Apply advanced debugging techniques, including the use of the Vivado analyzer tool for debugging an embedded processor system and HDL system simulation for processor-based designs
• Identify the steps involved in integrating a memory controller into an embedded system using the Cortex-A9 and MicroBlaze processors
• Integrate an interrupt controller and interrupt handler into an embedded design
• Design a flash memory-based system and boot load from off-chip flash memory
1. Hardware-Software Flow
Illustrates how design information generated during the hardware development process is moved into the SDK tool realm.
2. Zynq-7000 All Programmable SoC Architecture Overview
Overview of the Zynq-7000 All Programmable SoC architecture.
3. MicroBlaze Processor Architecture Overview
Overview of the MicroBlaze microprocessor architecture.
4. Zynq UltraScale+ MPSoC Architecture Overview
Overview of the Zynq UltraScale+ MPSoC architecture.
5. Debugging: Marking Nets
Reviews the process of marking nets to show which signals should be monitored without having to explicitly instantiate ILA cores.
6. Debugging: Hardware-Software Co-Debugging (Cross-Triggering)
Describes how to enable events in hardware to pause the software execution and breakpoints in software to cause an ILA trigger.
7. PS Peripherals – High-Speed: Gigabit Ethernet
Introduces the Gigabit Ethernet high-speed peripheral.
8. PS Peripherals – Low-Speed: Overview
Introduces the low-speed peripherals in the Zynq All Programmable SoC.
9. Sharing PS Resources (Hardware Perspective)
Illustrates from the hardware design perspective how a master in the PL can leverage resources within the PS.
10. Booting: PL
Introduces the concepts behind configuring the PL at boot.
1. Overview of Embedded Hardware Development
2. Hardware-Software Flow
3. Software Overview
4. Zynq-7000 All Programmable SoC Architecture Overview
5. MicroBlaze Processor Architecture Overview
6. Zynq UltraScale+ MPSoC Architecture Overview
7. Debugging: Hardware Introduction
8. Debugging: Marking Nets
9. Debugging: Hardware-Software Co-Debugging (Cross-Triggering)
10. Memory Types: Memory Overview
11. Memory Types: Block RAM Controllers
12. Memory Types: Static Memory Controllers
13. Memory Types: DDRx Memory Operation
14. Memory Types: Dynamic Memory Controller (Zynq-7000 Device)
15. Interrupt Concepts: Introduction to Interrupts
16. Interrupt Concepts: Interrupts and the Zynq-7000 Device
17. Interrupt Concepts: General Interrupt Controller
18. Interrupt Concepts: Interrupts and the MicroBlaze Processor
19. Interrupt Concepts: AXI Interrupt Controller for the MicroBlaze Processor
20. AXI Concepts: AXI Streaming Introduction
21. AXI Concepts: MicroBlaze Processor Streaming Ports
22. AXI Concepts: AXI Streaming FIFO
23. AXI Concepts: Connecting AXI IP
24. AXI Concepts: DMA
25. Zynq-7000 Device PS-PL Interface
26. PS Peripherals – High-Speed: USB
27. PS Peripherals – High-Speed: Gigabit Ethernet
28. PS Peripherals – Low-Speed: Overview
29. PS Peripherals – Low-Speed: CAN
30. PS Peripherals – Low-Speed: I2C
31. PS Peripherals – Low-Speed: SD/SDIO
32. PS Peripherals – Low-Speed: SPI
33. PS Peripherals – Low-Speed: UART
34. Utility Logic
35. Sharing PS Resources (Hardware Perspective)
36. Multi-Processor Hardware Architecture
38. Processor Caching and SCLR
39. Accelerator Coherency Port
40. Booting: Flow
41. Booting: PL
42. Booting: Flash Image Generation
43. QEMU: Introduction