ARM – CORTEX-A57 IMPLEMENTATION – ARM ARCHITECTURE V8

Course Outline:

1. OVERVIEW OF CORTEX-A57 [1-hour]
• Block diagram
• Memory interface that implements either an ACE or CHI interface
• ACP to connect a coherent DMA
• Coherent interface, studying examples of hardware coherency within a Cluster and between Clusters
• SoC architecture based on CCN-504 interconnect
• Implementation options

2. INTRODUCTION TO ARM ARCHITECTURE V8 [1-hour]
• Enhancement with regard to AArchv7
• General-purpose register file and the stack pointer in AArch64 state
• Register mapping between A32/T32 and A64
• Mapping of AArch64 System registers to the AArch32 System registers
• Process state, PSTATE

3. ARMv8 EXCEPTION [2 -hour]
• Four exception levels
• Definition of a precise exception
• Definitions of synchronous and asynchronous exceptions
• Exception Link Registers
• Current Exception Level register
• Register banking by exception level based on a new exception model
• Nesting on the same exception level
• Exception type and exception origin
• SPSR_EL1-3 when exception taken from AArch32 / Aarch64
• Syndrome registers used to provide a status information to the exception handler
• Status information when an Abort occurs
• Clarifying the differences between AArch32 and AArch64
• Exception return instruction
• Reset, requesting a warm reset

4. The ARMv8-A security model [1-hour]
• TrustZone implementation
• Security model when EL3 is using AArch64
• Trapping to EL3 using AArch64
• Disabling EL3, EL2, and EL1 execution of SMC instructions
• Cortex-A57 registers affected by CP15SDISABLE

5. INTERPROCESSING [1-hour]
• Managing two types of processes: 64-bit and 32-bit, switching on an exception
• Non secure space organization
• Saving the A32/T32 state when taking an exception leading to A64

6. VIRTUALIZATION  [1-hour]
• Similar implementation as V7-A with virtualization extensions
• The effect of implementing EL2 on the Exception model
• Virtual interrupts
• Trapping to EL2 using AArch64

7. INSTRUCTION PIPELINE [1-hour]
• Superscalar operation
• Predicted and non-predicted instructions
• Dynamic branch prediction with Branch Target Buffer (BTB)
• Global History Buffer (GHB) RAMs
• Return stack
• Indirect predictor
• BTB invalidation and context switches
• ISB instruction

8. MULTICORE [1-hour]
• Atomicity in the ARM architecture
• Synchronization and semaphores
• Shareability memory attributes
• Operation of the global monitor
• Load acquire / Store release instruction pair
• Use of WFE and SEV instructions by spin-locks
• Send Event Local instruction

9. MEMORY ACCESSES [1 -hour]
• Mixed-endian support
• Program counter and stack pointer alignment
• Observability and completion
• Ordering requirements
• Page attributes : Normal or Device
• Gathering, Reordering, Early Write Acknowledgement hint attributes
• Mismatched memory attributes
• Shareability and access limitations on the data barrier operations
• Memory barriers
• Cacheability, cache allocation hints, and cache transient hints

10. ARMv8 MMU SUPPORT [4-hour]
• LPAE enhancements to adapt to AArch64
• Supporting up to 48 bits of VA per TTBR
• Upper 8 bits of address configured for Tagged Pointers
• Access permission checking
• Hierarchical control of data access permissions
• Determining the valid address range
• Supporting up to 48 bits of IPA and PA spaces
• VMSAv8-64 address translation system
• Controlling address translation stages
• Memory translation granule size : 4-, 16- or 64-KB
• Descriptor page table organization, descriptor format
• Selection between TTBR0 and TTBR1
• Security state of translation table lookups
• Hierarchical control of Secure or Non-secure memory accesses
• Combining the stage 1 and stage 2 attributes
• TLB preload instructions
• TLB maintenance instructions in A64
• Cortex-A57 TLB implementation
• Detail of L1 and L2 TLBs of Cortex-A57
• Address Translation instructions in A64, perform stage 1 and 2 address translations as defined for EL0-3
• MMU faults
• Cortex-A57 Intermediate table walk caches