Price 4670 + VAT

Prerequisite:

Knowledge of ARM7/9.
This course does not include chapters on low level programming.

Lab Description:

Labs are run under RVDS

Related tutorials

• NEON programming
• VFP programming
• Thumb-2 programming

Course Goals and Objectives

This course is split into 3 important parts:
• Cortex-A8 architecture
• Cortex-A8 software implementation and debug
• Cortex-A8 hardware implementation.
MMU operation under Linux is described.
Interaction between level 1 caches, level 2 cache and main memory is studied through sequences.
The exception mechanism is detailed, indicating how virtualization enables the support of several operating systems.
The course also details the hardware implementation and provides some guidelines to design a SoC based on Cortex-A8.
An overview of the Coresight specification is provided prior to describing the debug related units.

Course Outline:

First day

1. ARM BASICS [1-hour]
• States and modes
• Benefit of register banking
• Exception mechanism
• Instruction sets
• Purpose of CP15

2. TRUSTZONE [1-hour]
• TrustZone conceptual view
• Secure to non secure permitted transitions
• Related CP15 registers
• L1 and L2 secure state indicators, memory partitioning
• Boot sequence

3. INTRODUCTION TO CORTEX-A8 [1-hour]
• Block diagram
• Highlighting the instruction path and the data path
• Operating modes
• Supported instruction sets
• Exceptions
• Configurable options

4. INSTRUCTION PIPELINE [1-hour]
• Superscalar pipeline operation
• Studying how instructions are processed step by step
• Instruction cycle timing
• Branch prediction mechanism, BTB and GHB usage
• Guidelines for optimal performance
• Return stack
• Instruction Memory Barrier
• Prefetch queue flush
• PMU related events

5. MEMORY MANAGEMENT UNIT [4-hour]
• MMU objectives
• Page sizes
• Address translation
• Page access permission, domain and page protection
• Page attributes, memory types
• Format of the external page descriptor table
• Software vs hardware tablewalk
• TLB organization
• TLB lockdown
• Utilization of microTLBs
• Abort exception, on-demand page mechanism
• MMU maintenance operations
• PMU related events
• Related CP15 registers

Second day

6. CORTEX-A8 LEVEL 1 AND LEVEL 2 CACHES [4-hour]
• Cache basics: organization, replacement algorithm, write policies, way-locking
– L1 cache organization
– Virtual indexing, physical tagging
– Hardware support for virtual aliasing conditions
– Parity protection
– Write buffer
– L1 caches software read for debug purposes
– PMU related events
– CP15 related registers
– L2 Cache organization
– Physical indexing, physical tagging
– L2 cache transfer policy
– Parity / ECC protection
– Write buffer
– L2 Preload Engine [PLE], programming the channels
– START, STOP and CLEAR commands
– L2 cache software read for debug purposes
– PMU related events
– CP15 related registers

7. AXI PROTOCOL [2-hour]
• Topology: direct connection, multi-master, multi-layer
• PL301 AXI interconnect
• Separate address/control and data phases
• AXI channels, channel handshake
• Support for unaligned data transfers
• Transaction ordering, out of order transaction completion
• Read and write burst timing diagrams
• Cortex-A8 external memory interface, ID encoding

8. HARDWARE IMPLEMENTATION [1-hour]
• Clock domains, CLK, PCLK, ATCLK
• Using clock enable to determine the ratio between input clock and operation clock
• Reset domains, power-on reset, debug and ETM reset
• Power control, dynamic power management
• Wait For Interrupt architecture
• AXI master interface attributes
• Static or leakage power management
• Debugging the processor while powered down
• Internal exclusive monitor, clarifying ldrex / strex instructions

Third day

9. PERFORMANCE MONITOR [1-hour]
• Event counting
– Selecting the event to be counted for the 4 counters
– Related interrupts
– Debugging a multi-core system with the assistance of the PMU

10. VECTORED INTERRUPT CONTROLLER [3-hour]
• Cortex-A8 exception management: enforcing a particular endian mode on exception entry, configuring FIQ to be non maskable, configuring the default exception handling state: ARM vs Thumb
• The 3 vector table base registers
• Interrupt virtualization
• Connection of an external interrupt controller
• Benefit of a Vectored interrupt controller
• Enabling interrupt nesting
• ARM PL192 VIC
• Description of the programming model
• Sequence required to clear the interrupt source
• Cascading two PL192s

11. LOW POWER MODES [1-hour]
• Voltage domains
• Run mode, standby mode, dormant mode
• Studying the sequence required to enter and exit dormant mode
• Communication to the power management controller
• Standby and wait for event signals, implementation in a multi-core system

12. CORESIGHT DEBUG UNITS [2-hour]
• Benefits of CoreSight
• Invasive debug, non-invasive debug, taking into account the secure attribute
• APBv3 debug interface
• Connection to the Debug Access Port
• Debug facilities offered by Cortex-A8
• Process related breakpoint and watchpoint
• Program counter sampling
• Event catching
• Debug Communication Channel
• ETM interface, connection to funnel
• Debugging while the processor is in shutdown or dormant mode
• Debug registers description
• Miscellaneous debug signals
• Cross-Trigger Interface, debugging a multi-core SoC

13. Summary

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