ARM – CORTEX-A9MP SOFTWARE IMPLEMENTATION

Course Outline:

First day

1. INTRODUCTION TO CORTEX-A9 [1-hour]
• Block diagram, 1 or 2 AXI master interfaces
• Cortex-A9 variants: single core vs multicore
• New memory-mapped registers in MPCore
• The 3 instruction sets
• Configurable options: cache size, Jazelle, NEON, FPU, PTM and IEM

2. ARM BASICS [1-hour]
• States and modes
• Benefit of register banking
• Exception mechanism
• Instruction sets
• Purpose of CP15

3. INSTRUCTION PIPELINE [2-hour]
• Superscalar pipeline operation, out-of-order operation
• Instruction cycle timing
• Branch prediction mechanism, BTAC and GHB usage
• Guidelines for optimal performance
• Return stack
• Predicted and non-predicted instructions
• Prefetch queue flush
• PMU related events

4. TRUSTZONE [2-hour]
• TrustZone conceptual view
• Secure to non secure permitted transitions
• Related CP15 registers
• L1 and L2 secure state indicators, memory partitioning
• Interrupt management when there is a mix of secure and non-secure interrupt sources
• Boot sequence
• Entering / exiting dormant mode

5. OS SUPPORT – SYNCHRONIZATION OVERVIEW [2-hour]
• Inter-Processor Interrupts
• Barriers
• Cluster ID
• Exclusive access monitor, implementing Boolean semaphores
• Global monitor
• Spin-lock implementation
• Using events

Second day

6. THUMB-2, THUMB-2EE AND ARM INSTRUCTION SETS  (V7-A) [2-hour]
• Introduction
• General points on syntax
• Data processing instructions
• Branch and control flow instructions
• Memory access instructions
• Exception generating instructions
• If…then conditional blocks
• Stack in operation
• Exclusive load and store instructions
• Accessing special registers
• Coprocessor instructions
• Interworking ARM and Thumb states
• Thumb-2EE extension for supporting interpreted languages
• Using handlers to manage NULL pointers and array index that are outside a programmable range
• Demonstration of assembly sequences aimed to understand this new instruction set

7. MEMORY MANAGEMENT UNIT [2-hour]
• MMU objectives
• Page sizes
• Address translation
• Page access permission, domain and page protection
• Page attributes, memory types
• Utilization of memory barrier instructions
• Format of the external page descriptor table
• Tablewalk
• TLB organization
• TLB lockdown
• Utilization of microTLBs
• Abort exception, on-demand page mechanism
• MMU maintenance operations
• Using a common page descriptor table in an SMP platform, maintaining coherency of multiple TLBs
• PMU related events
• Related CP15 registers

8. LEVEL 1 MEMORY SYSTEM [2-hour]
• Cache organization
• Virtual indexing, physical tagging for instruction cache ; physical indexing and tagging for data cache
• Supported maintenance operations
• Write-back write allocate cache allocation
• Memory hint instructions PLD, PLI, PLDW, data prefetching
• Describing transient cache related transactions: line fills and line eviction
• No lockdown support
• 4-entry 64-bit merging store buffer
• PMU related events

9.PL310 LEVEL 2 CACHE [2-hour]
• Cache configurability
• Exclusive mode operation when connected to Cortex-A9
• Understanding through sequences how cacheable information is copied from memory to level 1 and level 2 caches
• Transient operations, utilization of line buffers LFBs, LRBs, EBs and STBs
• Discarding a level 3 memory line load through merging writes into STBs
• TrustZone support
• Power management
• Cache event monitoring
• Memory mapped registers included in the cache controller
• Describing each maintenance operation
• Cache lockdown, implementation of a small memory by a boot program
• Initialization sequence
• Interrupt management

Third day

10.HARDWARE COHERENCY [1-hour]
• Snooping basics
– Snoop requests
– Snoop Control Unit: cache-to-cache transfers
– MOESI state machine
– Address filtering
– Understanding through sequences how data coherency is maintained between L2 memory and L1 caches
– Accelerator Coherency Port: connecting a DMA channel that uses this port to enforce coherency of data it is transmitting
– Enabling coherency mode

11. PERFORMANCE MONITOR [1-hour]
• Event counting
• Selecting the event to be counted for the 6 counters
• Related interrupts
• Debugging a multi-core system with the assistance of the PMU