ARM CORTEX-A9MP SYSTEM DESIGN

Course Outline:

1. INTRODUCTION TO CORTEX-A9 [1-hour]
• Block diagram, 1 or 2 AXI master interfaces
• Cortex-A9 variants: single core vs multicore
• New memory-mapped registers in MPCore
• The 3 instruction sets
• Configurable options: cache size, Jazelle, NEON, FPU, PTM and IEM

2. ARM BASICS [1-hour]
• States and modes
• Benefit of register banking
• Exception mechanism
• Instruction sets
• Purpose of CP15

3. INSTRUCTION PIPELINE [2-hour]
• Superscalar pipeline operation, out-of-order operation
• Instruction cycle timing
• Branch prediction mechanism, BTAC and GHB usage
• Guidelines for optimal performance
• Return stack
• Predicted and non-predicted instructions
• Prefetch queue flush
• PMU related events

4. TRUSTZONE [2-hour]
• TrustZone conceptual view
• Secure to non secure permitted transitions
• Related CP15 registers
• L1 and L2 secure state indicators, memory partitioning
• Interrupt management when there is a mix of secure and non-secure interrupt sources
• Boot sequence
• Entering / exiting dormant mode

5. INTRODUCTION TO MULTI-CORE SYSTEMS [2-hour]
• AMP vs SMP
• Inter-Processor Interrupts
• Boot sequence
• Cluster ID
• Exclusive access monitor, implementing Boolean semaphores
• Global monitor
• Spin-lock implementation
• Using events
• Indicating the effect of Multi Core on debug interfaces
• Basic concepts of RTOS supporting A9 SMP architecture

6. THUMB-2 INSTRUCTION SET (V7-A) [2-hour]
• Introduction
• General points on syntax
• Data processing instructions
• Branch and control flow instructions
• Memory access instructions
• Exception generating instructions
• If…then conditional blocks
• Stack in operation
• Exclusive load and store instructions
• Accessing special registers
• Coprocessor instructions
• Memory barriers and synchronization
• Interworking ARM and Thumb states
• Demonstration of assembly sequences aimed to understand this new instruction set

7. MEMORY MANAGEMENT UNIT [3-hour]
• MMU objectives
• Page sizes
• Address translation
• Page access permission, domain and page protection
• Page attributes, memory types
• Utilization of memory barrier instructions
• Format of the external page descriptor table
• Tablewalk
• TLB organization
• TLB lockdown
• Utilization of microTLBs
• Abort exception, on-demand page mechanism
• MMU maintenance operations
• Using a common page descriptor table in an SMP platform, maintaining coherency of multiple TLBs
• PMU related events
• Related CP15 registers

8. LEVEL 1 MEMORY SYSTEM [2-hour]
• Cache organization
• Virtual indexing, physical tagging for instruction cache ; physical indexing and tagging for data cache
• Supported maintenance operations
• Write-back write allocate cache allocation
• Memory hint instructions PLD, PLI, PLDW, data prefetching
• Describing transient cache related transactions: line fills and line eviction
• No lockdown support
• 4-entry 64-bit merging store buffer
• PMU related events

9. HARDWARE COHERENCY [1-hour]
• Snooping basics: CLEAN, CLEAN & INVALIDATE and INVALIDATE snoop requests
• Snoop Control Unit: cache-to-cache transfers
• MOESI state machine
• Address filtering
• Understanding through sequences how data coherency is maintained between L2 memory and L1 caches
• Accelerator Coherency Port: connecting a DMA channel that uses this port to enforce coherency of data it is transmitting
• Enabling coherency mode

10. AMBA 3 [2-hour]
• AXI
– Topology: direct connection, multi-master, multi-layer
– PL301 AXI interconnect
– Separate address/control and data phases
– AXI channels, channel handshake
– Support for unaligned data transfers
– Transaction ordering, out of order transaction completion
– Read and write burst timing diagrams
– Cortex-A9 external memory interface, ID encoding
• APB 3