ARM – CYCLONE-V CORTEX-A9 HARD PROCESSOR SYSTEM

Course Outline:

First day

INTRODUCTION TO CORTEX-A9 [1-hour]
• Block diagram, 1 or 2 AXI master interfaces
• Cortex-A9 variants: single core vs multicore
• New memory-mapped registers in MPCore
• The 3 instruction sets
• Instantiated options: cache size, Jazelle, NEON, FPU, PTM and IEM
CYCLONE-V OVERVIEW [1-hour]
• Hard Processor System block diagram
• FPGA portion
• On-chip memories
• Possible boot scenario
• HPS-FPGA interfaces
• Address mappings, translation when implementing ACP

CLOCK AND RESET MANAGERS [1-hour]
• Reset sources
• Hardware sequenced resets
• Block diagram, integrated three PLLs
• Clock usage by module
• Main clock group
• Cortex-A9 clock scaling
• Software managed clocks

BOOTING AND CONFIGURATION [1-hour]
• Boot sequence
• Selecting the interface from which the boot code will be loaded
• Indirect vs direct code execution
• Initial software, boot loader
• Initial software image layout
• Independent HPS booting and FPGA configuration

AMBA 4 [2-hour]
• AXI
– Topology: direct connection, multi-master, multi-layer
– Separate address/control and data phases
– AXI channels, channel handshake
– Support for unaligned data transfers
– Transaction ordering, out of order transaction completion
– Read and write burst timing diagrams
– Cortex-A9 external memory interface, ID encoding
– NIC-301 AXI interconnect
• APB 3

MEMORY MANAGEMENT UNIT [2-hour]
• MMU objectives
• Page sizes
• Address translation
• Page access permission, domain and page protection
• Page attributes, memory types
• Utilization of memory barrier instructions
• Format of the external page descriptor table
• Tablewalk
• TLB organization
• TLB lockdown
• Utilization of microTLBs
• Abort exception, on-demand page mechanism
• MMU maintenance operations
• Using a common page descriptor table in an SMP platform, maintaining coherency of multiple TLBs
• PMU related events
• Related CP15 registers

Second day

LEVEL 1 MEMORY SYSTEM [2-hour]
• Cache organization
– Virtual indexing, physical tagging for instruction cache ; physical indexing and tagging for data cache
– Supported maintenance operations
– Write-back write allocate cache allocation
– Memory hint instructions PLD, PLI, PLDW, data prefetching
– Describing transient cache related transactions: line fills and line eviction
– No lockdown support
– 4-entry 64-bit merging store buffer
– PMU related events

HARDWARE COHERENCY [2-hour]
• Snooping basics: CLEAN, CLEAN & INVALIDATE and INVALIDATE snoop requests
• Snoop Control Unit: cache-to-cache transfers
• MOESI state machine
• Address filtering
• Understanding through sequences how data coherency is maintained between L2 memory and L1 caches
• Accelerator Coherency Port: connecting a DMA channel that uses this port to enforce coherency of data it is transmitting
• Enabling coherency mode

PL310 LEVEL 2 CACHE [2-hour]
• Cache configurability
• AXI interface characteristics
• Exclusive mode operation when connected to Cortex-A9
• Understanding through sequences how cacheable information is copied from memory to level 1 and level 2 caches
• Transient operations, utilization of line buffers LFBs, LRBs, EBs and STBs
• Discarding a level 3 memory line load through merging writes into STBs
• TrustZone support
• Power management
• Cache event monitoring
• Memory mapped registers included in the cache controller
• Describing each maintenance operation
• Cache lockdown, implementation of a small memory by a boot program
• Initialization sequence
• Interrupt management
SYSTEM INTERCONNECT [2-hour]
• Interconnect block diagram, master-to-slave connectivity matrix
• Bridge to APB, L4 slaves
• L3 main switch
• QoS, arbitration policies
• Cyclic dependencies avoidance schemes
• Address remapping
• ACP ID mapper
• HPS-to-FPGA AXI bridge
• FPGA-to-HPS AXI bridge, directly accessing SDRAM from FPGA masters with or without hardware cache coherency
• Clarifying the conditions for an FPGA IP to use hardware coherency

Third day

MEMORY CONTROLLERS [3-hour]
• On Chip RAM
– ECC support
• Integrated DDR3 controller
– Introduction to DDR3, write levelling, ZQ calibration, reset
– ECC control
– Parameterizing the controller according to DDR3 device timings
– FPGA-to-HPS SDRAM port utilization, 64-, 128- or 256-bit Avalon or AXI ports
– Multiport scheduling
– AXI global monitor
– Command reordering
• NAND flash controller
– Discovery and initialization
– Data DMA
– ECC control
• SD/MMC controller
– Card detection and initialization
– Booting from SD/MMC
– Integrated descriptor-based DMA
– 4-KB data FIFO
– Error management
• Quad SPI flash controller
– Direct access and indirect access modes
– Using a memory-mapped interface to automatically initiate flash page reads / writes
– XIP flash device
– Local memory buffer
– STIG operation

CORTEX-A9 HARDWARE IMPLEMENTATION [2-hour]
• Clock domains
• Reset domains, power-on reset, debug and Data Engine logic reset
• Power control, dynamic power management
• Wait For Interrupt architecture
• AXI master interface attributes
• Level 2 memory interface: AXI read & write issuing capability
• Exclusive L2 cache
• AXI sideband information