Date 24,31.12.2019+1.1.2020
Price 4585+ VAT /15 Tcs
DURATION 6 Half Days

Course Overview

The course provides a thorough introduction to the Vivado® High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.

Level:

DSP 3

Who should attend?

Software and hardware engineers looking to utilize high-level synthesis

Prerequisite:

• C, C++, or System C knowledge
• High-level synthesis for software engineers OR high-level synthesis for hardware engineers

Software Tools:

• Vivado System Edition 2017.3
• SDx™ development environment 2017.1
• MATLAB R2017a

Hardware:

• Architecture: Zynq®-7000 All Programmable SoC and 7 series FPGAs*
• Demo board: Zynq-7000 All Programmable SoC ZC702 or Zed board and Kintex®-7 FPGA KC705 board*

Skills Gained: After completing this training, you will be able to:

• Enhance productivity by using the Vivado HLS tool
• Describe the high-level synthesis flow
• Use the Vivado tool HLS for a first project
• Identify the importance of the testbench
• Use directives to improve performance and area and select RTL interfaces
• Identify common coding pitfalls as well as methods for improving code for RTL/hardware
• Perform system-level integration of blocks generated by the Vivado HLS tool
• Describe how to use OpenCV functions in the Vivado HLS tool

Lab Description:

Lab Description– Basics of the Vivado HLS Tool
Explore the basics of high-level synthesis and the Vivado HLS tool.
– Vivado HLS Tool Command Line Interface
Describes the Vivado HLS tool flow in command prompt mode.
– Block-Level Protocols
Explains the different types of block-level protocols abstracted by the Vivado HLS tool.
– Port-Level Protocols
Describes the port-level interface protocols abstracted by the Vivado HLS tool from the C design.
– Port-Level Protocols: Memory Interfaces
Describes the Memory Interface port-level protocols (such as BRAM, FIFO) abstracted by the Vivado HLS tool from the C design.
– Pipeline for Performance: PIPELINE
Describes the PIPELINE directive for improving the throughput of a design.
– Pipeline for Performance: DATAFLOW
Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to executes as soon as possible.
– Optimizing Structures for Performance
Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance.
– Improving Area
Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.
– Introduction to HLx Design Flow
Describes the traditional RTL flow versus the Vivado HLx design flow.
– Vivado HLS Tool: C Code
Describes the Vivado HLS tool support for the C/C++ languages, as well as arbitrary precision data types.

Course Outline:

1. Introduction to High-Level Synthesis
2. Basics of the Vivado HLS Tool
3. Design Exploration with Directives
4. Vivado HLS Tool Command Line Interface
5. Introduction to HLS UltraFast Design Methodology
6. Introduction to I/O Interfaces
7. Block-Level Protocols
8. Port-Level Protocols
9. Port-Level Protocols: AXI4 Interfaces
10. Port-Level Protocols: Memory Interfaces
11. Port-Level Protocols: Bus Protocol
12. Pipeline for Performance: PIPELINE
13. Pipeline for Performance: DATAFLOW
14. Optimizing Structures for Performance
15. Data Pack and Data Dependencies
16. Vivado HLS Tool Default Behavior: Latency
17. Reduce Latency
18. Improving Area
19. Introduction to HLx Design Flow
20. HLS vs. SDSoC Development Environment Flow
21. Vivado HLS Tool: C Code
22. Hardware Modeling
23. OpenCV Libraries
24. Pointers

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