Price 1660 + VAT /5 Tcs
DURATION 1 Day

Course Overview

C-based coding is increasingly used for the modeling and high-level synthesis of hardware components. This course provides hardware engineers with sufficient knowledge of C-programming techniques for Vivado™ HLS to take advantage of Xilinx FPGAs. Learn high-level synthesis best practices, methodology, and subtleties of C-based coding for hardware modeling, synthesis, and verification.

Level:

DSP 3

Who should attend?

Hardware engineers looking to utilize high-level synthesis

Prerequisite:

• C, C++, or System C knowledge
• HDL knowledge
• Hardware design

Software Tools:
• Vivado System Edition 2012.2

Hardware Tools:
• Architecture: Zynq™-7000 All Programmable SoC and 7 series FPGAs*
• Demo board: None

Skills Gained: After completing this training, you will be able to:
• Describe the difference between software programming and hardware design
• Model and simulate hardware components using C
• Code hardware components in C for high-level synthesis

Lab Description:

Lab 1: High-Level Synthesis of a C Model – Use various techniques and directives in Vivado HLS to improve design performance. The design under consideration accepts an image in a (custom) RGB format, converts it to the Y’UV color space, and applies a filter to the Y’UV image and converts it back to RGB.

Lab 2: Creating a C-based Test Bench – Develop a verification environment used for testing a C-based design and verification in Vivado HLS. The design under consideration is the same design used in the previous lab, a Y’UV filter.

Course Outline:

1. Introduction to Software Design for Hardware Designers

2. C-based Algorithmic Coding for Hardware
Lab 1: High-Level Synthesis of a C Model

3. C-based Test Bench Coding
Lab 2:
Creating a C-based Test Bench

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