Design Closure Techniques

Start Date: Please contact us

Price 4,228 ILS

/ 12 Tcs

DURATION 2 Days

Course Overview

Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, timing, and power simultaneously to achieve faster time-to-market results. The emphasis of this course is on:

Defining what design closure is and describing the three pillars of design closure (functional closure, timing closure, and power closure)
Using recommended coding techniques
Creating a test bench for functional verification
Applying initial design checks and reviewing timing summary and methodology reports for a design
Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
Performing quality of results (QoR) assessments at different stages to improve the QoR score
Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
Reviewing the importance of power closure and device selection
Estimating power consumption by using the Vivado® Design Suite Power Report utility and performing power optimization on a design
Identifying Versal® ACAP power and thermal solutions
Utilizing architecture features to improve a design’s power consumption

What’s New for 2022.2

New modules:

Platform Creation for the Versal ACAP
Versal ACAP: Power Design Manager
All labs have been updated to the latest software versions

Level:

FPGA 2

Who should attend?

Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques related to functional, timing, and power closure

Prerequisite:

Basic knowledge of FPGA and SoC architecture and HDL coding techniques
Basic knowledge of the Vivado Design Suite

Software Tools:

Vivado® Design Suite 2022.2

Hardware:

Architecture: UltraScale™ FPGAs and Versal ACAPs

Skills Gained: After completing this training, you will be able to:

Describe what is design closure is as well as its three pillars.
Create a test bench for functional verification.
Resolve setup and hold violations by reducing logic delay and net delay.
Improve clock skew and clock uncertainty.
Identify clock domain crossings (CDC) and scenarios that require synchronization circuits
Perform QoR assessment at different stages and improve the QoR score.
Implement Intelligent Design Runs (IDR)
Apply the power closure flow for better time to market.
Estimate power consumption by using the Xilinx Power Estimator (XPE)
Leverage the Power Design Manager tool for power estimation.
Describe Versal ACAP power and thermal solutions.
Perform power optimization on a design

Course Outline:

Day 1

Introduction

Introduction to Design Closure Defines what design closure is and identifies the three pillars of design closure.

Functional Closure

HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design.
Platform Creation for the Versal ACAP
Reviews the different Versal ACAP design flows and covers the platform creation process using the Vivado IP integrator, RTL, HLS, and Vitis™ environment.
Behavioral Simulation
Describes the process of behavioral simulation and the simulation options available in the Vivado IDE.
Creating a Test Bench
Describes the design components of a test bench, the different test bench types and how a self-checking test bench can be constructed.

Timing Closure

Static Timing
Analysis (STA) Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA).
UltraFast Design Methodology: Timing Closure
Provides an overview of the various stages of the UltraFast Design Methodology for timing closure.
Baselining
Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing. (Lecture + Lab)
Setup and Hold Violation Analysis
Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis.
Reducing Logic Delay
Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives.
Reducing Net Delay
Reviews different techniques to reduce congestion and net delay.
Improving Clock Skew
Describes how to apply various techniques to improve clock skew.
Improving Clock Uncertainty
Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. (Lecture + Lab)
QoR Reports Overview
Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. (Lecture + Lab)

Day 2

Timing Closure (continued)

Clock Domain Crossing (CDC) and Synchronization Circuits
Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits.
Intelligent Design Runs (IDR)
Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. (Lecture + Lab)

Power Closure

Understanding Design Power
Outlines the types of design power, describes the power closure flow, and identifies methods for bringing down the power of a device. (Lecture + Lab)
Power Estimation Using XPE
Demonstrates how to estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. (Lecture + Lab)
Versal ACAP: Power Design Manager
Discusses using the new Power Design Manager tool, including import and export functions. (Lecture + Lab)
Power and Thermal Solutions for the Versal ACAP
Discusses the power domains in the Versal ACAP as well as power optimization and analysis techniques. Thermal design challenges are also covered.
Design Power Constraints
Describes what design power constraints are and how to use the Power Constraints Advisor tool. Power rail constraints are also covered.
Power Management Techniques
Identifies techniques used for low power design.
Power Analysis and Optimization
Covers how to use report power commands to estimate power consumption. (Lecture + Lab)