Price 3145 + VAT /10 Tcs
DURATION 2 Days

Course Overview

Attending the Designing for Performance class will help you create more efficient FPGA designs. This course will enable you to optimize your design for usage in a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Level:

FPGA3

Who should attend?

FPGA designers interested in FPGA design optimization with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools.

Prerequisite:

FPGA designers interested in FPGA design optimization with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools.

Software Tools:

Xilinx ISE Design Suite: Logic or System Edition 14.7

Hardware:

Architecture: 7 series FPGAs*

  • Demo board: Kintex™-7 KC705 board*

 

Skills Gained: After completing this training, you will be able to:

After completing this training, you will be able to:

  • Describe the architectural features of the 7 series FPGAs
  • Create and integrate cores into your design flow by using the CORE Generator™ software system
  • Describe the clocking features of the 7 series FPGAs and how they can be used to improve performance
  • Increase performance by duplicating registers and pipelining
  • Increase system reliability by adding an appropriate synchronization circuit
  • Describe different synthesis options and how they can improve performance
  • Describe a flow for obtaining timing closure
  • Pinpoint design bottlenecks by using timing reports
  • Apply advanced timing constraints to meet your performance goals
  • Use advanced implementation options to increase design performance

Lab Description:

 Lab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool.  Instantiate these cores and other clock resources and implement the design.

Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results.

Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.

Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.

Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and the multiple run feature.

Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.

Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging

Recommended RELs

Basic HDL Coding Techniques (part 1 and part 2)

  • Power Estimation

 

Course Outline:

1. Review of Essentials of FPGA Design
2. Designing with FPGA Resources
3. CORE Generator Software System
4. Basic FPGA Clock Resources
5. Virtex-6 and Spartan-6 FPGA Clock Resources
6. Lab 1:
Designing with FPGA Resources
7. FPGA Design Techniques
8. Synthesis Techniques
9. Lab 2 :
Synthesis Techniques
10. Achieving Timing Closure
11. Lab 3 :
Review of Global Timing Constraints
12. Path-Specific Timing Constraints, Part 1
13. Path-Specific Timing Constraints, Part 2
14. Lab 4 :
Achieving Timing Closure
15. Advanced Implementation Options
16. Lab 5
: Designing for Performance
17. Lab 6 : FPGA Editor Demo (optional)
18. ChipScope Pro Software (optional)
19. Lab 7 :
ChipScope Pro Software (optional)

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