Date 08-09.11.19
Price 3145 + VAT /10 Tcs
DURATION 2 Days

Course Overview

This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow.
For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.

Level:

FPGA 1

Who should attend?

Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado® Design Suite

Prerequisite:

• Basic knowledge of the VHDL or Verilog language
• Digital design knowledge

Software Tools:

• Vivado System Edition 2017.3

Hardware:

• Architecture: UltraScale™ and 7 series FPGAs*
• Demo board (optional): Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*

Skills Gained: After completing this training, you will be able to:

• Use the New Project Wizard to create a new Vivado IDE project
• Describe the supported design flows of the Vivado IDE
• Generate a DRC report to detect and fix design issues early in the flow
• Use the Vivado IDE I/O Planning layout to perform pin assignments
• Explore synthesis and implementation options and directives
• Synthesize and implement the HDL design
• Apply clock and I/O timing constraints and perform timing analysis
• Describe the “baselining” process to gain timing closure on a design
• Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
• Use the Vivado logic analyzer and debug flows to debug a design

Lab Description:

– Vivado Design Suite Project Mode
  Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
– Synthesis and Implementation
Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate
and download the bitstream to the demo board.
– Basic Design Analysis in the Vivado IDE
Use the various design analysis features in the Vivado Design Suite.
– Vivado Design Rule Checks
Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations.
– Vivado Design Suite I/O Pin Planning
Use the I/O Pin Planning layout to perform pin assignments in a design.
– Vivado IP Flow
Customize IP, instantiate IP, and verify the hierarchy of your design IP.
– Introduction to Clock Constraints
Apply clock constraints and perform timing analysis.
– I/O Constraints and Virtual Clocks
Apply I/O constraints and perform timing analysis.
– Timing Constraints Wizard
Use the Timing Constraints Wizard to apply missing timing constraints in a design.
– Xilinx Power Estimator Spreadsheet
Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by
XPE.
– Introduction to the Tcl Environment
Introduces Tcl (tool command language).

Course Outline:

1. Introduction to FPGA Architecture, 3D IC, SoC
    Overview of FPGA architecture, SSI technology, and SoC device architecture.
2. UltraFast Design Methodology: Board and Device Planning
Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
3. HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design.
4. Introduction to Vivado Design Flows
Introduces the Vivado design flows: the project flow and non-project batch flow.
5. Vivado Design Suite Project Mode
6. Behavioral Simulation

Performs behavioral simulation for your design.
7. Synthesis and Implementation
8. Basic Design Analysis in the Vivado IDE
9. Vivado Design Suite I/O Pin Planning
10. Vivado IP Flow
11. Introduction to Clock Constraints
12. Generated Clocks

Use the report clock networks report to determine if there are any generated clocks in a design.
13. I/O Constraints and Virtual Clocks
14. Timing Constraints Wizard
15. Introduction to Vivado Reports

Generate and use Vivado timing reports to analyze failed timing paths.
16. Setup and Hold Timing Analysis
Understand setup and hold timing analysis.
17. Xilinx Power Estimator Spreadsheet
18. Introduction to FPGA Configuration

Describes how FPGAs can be configured.
19. Introduction to the Vivado Logic Analyzer
Overview of the Vivado logic analyzer for debugging a design.
20. Introduction to Triggering
Introduces the trigger capabilities of the Vivado logic analyzer.
21. Debug Cores
Understand how the debug hub core is used to connect debug cores in a design.
22. Introduction to the Tcl Environment
23. Using Tcl Commands in the Vivado Design Suite Project Flow

Explains what Tcl commands are executed in a Vivado Design Suite project flow.
24. Tcl Syntax and Structure
Understand the Tcl syntax and structure.

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