Designing FPGAs Using the Vivado Design Suite 1
Start Date: 08/05/2025
Course Overview
This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow for those uninitiated to FPGA design
This course helps in creating a Vivado Design Suite project with source files, simulating a design and synthesizing and implementing.
Level:
FPGA 1Who should attend?
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design SuitePrerequisite:
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge
Software Tools:
- Vivado® Design Suite 2021.1
Skills Gained: After completing this training, you will be able to:
- Use the New Project Wizard to create a new Vivado IDE project
- Describe the supported design flows of the Vivado IDE
- Generate a DRC report to detect and fix design issues early in the flow
- Synthesize and implement an HDL design
Lab Description:
– Vivado Design Suite Project-Based Mode
Introduces project-based mode in the Vivado Design Suite, including creating a project, adding files to a project, exploring the Vivado IDE, and simulating a design
– Vivado Synthesis and Implementation and Bitstream Generation
Reviews creating timing constraints according to the design scenario, synthesizing and implementing the design, and, optionally, generating and downloading a bitstream to a demo board
– Vivado Design Rule Checks
Illustrates how to run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations.
– Timing Simulation
Simulate the design post-implementation to verify that a design works properly on hardware.
Course Outline:
- Introduction to FPGAs
Provides an overview of FPGA architecture and describes the advantages, applications, and major building blocks of FPGAs. - FPGA & Adaptive SoC Families
Introduces 7 series and UltraScale™ FPGAs, stacked silicon interconnect-based 3D IC devices, Zynq®-7000 SoCs, Zynq UltraScale+™ MPSoCs, and Adaptive Compute Acceleration Platforms (ACAPs). - Introduction to the Vivado Design Suite
Describes various design flows and the role of the Vivado IDE in the flow. - Vivado Design Suite Project-Based Mode
- RTL Development
Covers RTL and the RTL design flow, recommended coding guidelines, using control signals, and recommendations on resets - Behavioral Simulation
Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. - Vivado Synthesis and Implementation and Bitstream Generation
- Introduction to Vivado Reports
Demonstrates generating and using Vivado timing reports to analyze failed timing paths - Timing Simulation
