Date 26,27.11+3,4.12.2019
Price 4635 + VAT /15 Tcs
DURATION 4 Days

Course Overview

This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Level:

FPGA 2

Who should attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisite:

• Designing FPGAs Using the Vivado Design Suite 1 course• Working HDL knowledge (VHDL or Verilog)
• Digital design experience

Software Tools:

• Vivado System Edition 2017.3

Hardware:

• Architecture: UltraScale™ and 7 series FPGAs*
• Demo board (optional): Kintex®-7 FPGA KC705 board*

Skills Gained: After completing this training, you will be able to:

• Identify synchronous design techniques
• Build resets into your system for optimum reliability and design speed
• Create a Tcl script to create a project, add sources, and implement a design
• Describe and use the clock resources in a design
• Create and package your own IP and add to the Vivado IP catalog to reuse
• Use the Vivado IP integrator to create a block design
• Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
• Describe how power analysis and optimization is performed
• Describe the HDL instantiation flow of the Vivado logic analyzer

Lab Description:

– Resets
  Investigates the impact of using asynchronous resets in a design.
– Scripting in Vivado Design Suite Project Mode
Explains how to write Tcl commands in the project-based flow for a design.
– Clocking Resources
Describes various clock resources, clocking layout, and routing in a design.
– Creating and Packaging Custom IP
Create your own IP and package and include it in the Vivado IP catalog.
– Designing with the IP Integrator
Use the Vivado IP integrator to create the uart_led subsystem.
– Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing.
– Power Analysis and Optimization Using the Vivado Design Suite
Use report power commands to estimate power consumption.
– HDL Instantiation Debug Probing Flow
Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic  analyzer.
– Design Analysis Using Tcl Commands
Analyze a design using Tcl commands.

Course Outline:

1. UltraFast Design Methodology: Design Creation and Analysis
  Overview of the methodology guidelines covered in this course.
2. Synchronous Design Techniques
Introduces synchronous design techniques used in an FPGA design.
3. Resets
4. Register Duplication

Use register duplication to reduce high fanout nets in a design.
5. Scripting in Vivado Design Suite Project Mode
6. Clocking Resources
7. I/O Logic Resources

Overview of I/O resources and the IOB property for timing closure.
8. Creating and Packaging Custom IP
9. Using an IP Container

Use a core container file as a single file representation for an IP.
10. Designing with the IP Integrator
11. Timing Constraints Editor

Introduces the timing constraints editor tool to create timing constraints.
12. Report Clock Networks
Use report clock networks to view the primary and generated clocks in a design.
13. Timing Summary Report
Use the post-implementation timing summary report to sign-off criteria for timing closure.
14. Clock Group Constraints
Apply clock group constraints for asynchronous clock domains.
15. Introduction to Timing Exceptions
16. Power Analysis and Optimization Using the Vivado Design Suite
17. Configuration Process

Understand the FPGA configuration process, such as device power up, CRC check, etc.
18. HDL Instantiation Debug Probing Flow
19. Design Analysis Using Tcl Commands

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