Price 4635 + VAT /15 Tcs
DURATION 3 Days

Course Overview

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL
coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced
capabilities of the Vivado logic analyzer.

Level:

FPGA 3

Who should attend?

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite

Prerequisite:

• Designing FPGAs Using the Vivado Design Suite 1 course
• Designing FPGAs Using the Vivado Design Suite 2 course
• Intermediate HDL knowledge (VHDL or Verilog)
• Solid digital design background

Software Tools:

Vivado Design or System Edition 2017.3

Hardware:

• Architecture: UltraScale™ and 7 series FPGAs*
• Demo board: Kintex®-7 FPGA KC705 board*

Skills Gained: After completing this training, you will be able to:

• Employ good alternative design practices to improve design reliability
• Define a properly constrained design
• Apply baseline constraints to determine if internal timing paths meet design timing objectives
• Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
• Increase performance by utilizing FPGA design techniques
• Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
• Describe how to enable remote debug

Lab Description:

1. Baselining
Use Xilinx-recommended baselining procedures to progressively meet timing closure.
2. Pipelining
Use pipelining to improve design performance.
3. Inference
Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
4. Revision Control Systems in the Vivado Design Suite
Use version control systems with Vivado design flows.
5. Timing Simulation
Simulate the design post-implementation to verify that a design works properly on hardware.
6. Synchronization Circuits
Use synchronization circuits for clock domain crossings.
7. Dynamic Power Estimation Using Vivado Report
Power

Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
8. Netlist Insertion Debug Probing Flow
Covers the netlist insertion flow of the debug using the Vivado logic analyzer.
9. Sampling and Capturing Data in Multiple Clock Domains
Overview of debugging a design with multiple clock domains that require multiple ILAs.
10. Debug Flow in an IP Integrator Block Design
Insert the debug cores into IP integrator block designs.
11. Remote Debugging Using the Vivado Logic Analyzer
Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.
12. Manipulating Design Properties Using Tcl
Query your design and make pin assignments by using various Tcl commands

Course Outline:

1. UltraFast Design Methodology:
Implementation Introduces the methodology guidelines covered in this course.
2. Vivado Design Suite Non-Project Mode
Create a design in the Vivado Design Suite non-project mode.
3. Baselining
4. Pipelining
5. Inference
6. Revision Control Systems in the Vivado Design Suite
7. Timing Simulation
8. Synchronization Circuits
9. Report Clock Interaction

Use the clock interaction report to identify interactions between clock domains.
10. Report Datasheet
Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
11. Dynamic Power Estimation Using Vivado Report Power
12. Netlist Insertion Debug Probing Flow
13. Sampling and Capturing Data in Multiple Clock Domains
14. JTAG to AXI Master Core

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