Designing with Multi-Gigabit Serial I/O
Start Date: 07/05/2025
Course Overview
Learn how to employ GTP and GTX serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Level:
Connectivity 3Who should attend?
FPGA designers and logic designersPrerequisite:
• Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
• Familiarity with logic design (state machines and synchronous design)
• Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
• Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Software Tools:
• Vivado® System Edition 2015.1
• Mentor Graphics QuestaSim simulator 10.3d
Hardware:
• Architecture: 7 series FPGAs*
• Demo board: Kintex™-7 FPGA KC705 board*
Skills Gained: After completing this training, you will be able to:
• Describe and utilize the ports and attributes of the serial transceiver in 7 series FPGAs
• Effectively utilize the following features of the gigabit transceivers:
– 8B/10B and other encoding/decoding, comma detection, clock correction, and channel bonding
– Pre-emphasis and linear equalization
• Use the 7 Series FPGAs Transceivers Wizard to instantiate GTX primitives in a design
• Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design
Lab Description:
Lab 1: 8B/10B Encoding and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.
Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences on the TX and RX clocks.
Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.
Lab 5: Transceiver Core Generation – Use the 7 Series FPGAs Transceivers Wizard to create instantiation templates.
Lab 6: Simulation – Simulate the transceiver IP using the IP example design.
Lab 7: Implementation – Implement the transceiver IP using the IP example design.
Lab 8: 64B/66B Encoding – Generate a 64B/66B core by using the 7 Series FPGAs Transceivers Wizard, simulate the design, and analyze the results.
Lab 9: Transceiver Debugging – Debug the transceiver IP using the IP example design and Vivado debug cores.
Lab 10: IBERT Lab – Create an IBERT design to verify physical links.
Lab 11: System Lab – Perform all design steps from planning the design, generating the core, integrating the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.
Course Outline:
1. 7 Series FPGAs Overview
2. 7 Series FPGAs Transceivers Overview
3. 7 Series FPGAs Transceivers Clocking and Resets
4. 8B/10B Encoder and Decoder
5. Lab 1: 8B/10B Encoding and Bypass
6. Commas and Deserializer Alignment
7. Lab 2: Commas and Data Alignment
8. RX Elastic Buffer and Clock Correction
9. Lab 3: Clock Correction
10. Channel Bonding
11. Lab 4: Channel Bonding
12. Transceiver Wizard Overview
13. Lab 5: Transceiver Core Generation
14. Lab 6: Simulation
15. Transceiver Implementation
16. Lab 7: Implementation
17. Physical Media Attachments
18. 64B/66B Encoding and the Gearbox
19. Lab 7: 64B/66B Encoding
20. Transceiver Board Design Considerations
21. Transceiver Test and Debugging
22. Lab 9: Transceiver Debugging
23. Lab 10: IBERT Lab
or
24. Lab 11: System Lab
25. Transceiver Application Examples
