Price 3145 + VAT /10 Tcs
DURATION 2 Days

Course Overview

Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express® technology, analog to digital converters and gigabit transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most

Level:

FPGA3

Who should attend?

For those who have taken the Essentials of FPGA Design course.

Prerequisite:

Essentials of FPGA Design course

  • Intermediate VHDL or Verilog knowledge Software Tools: ISE Design Suite 13.1

 

Software Tools:

Xilinx Vivado™ System Edition 2012.2

Hardware:

Artix-7, Kintex-7, and Virtex®-7 FPGAs
Demo board: None

Skills Gained: After completing this training, you will be able to:

After completing this training, you will be able to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the 7 series FPGAs
  • Specify the CLB resources and the available slice configurations for the 7 series FPGAs
  • Define the block RAM, FIFO, and DSP resources available for the 7 series FPGAs
  • Properly design for the I/O block and SERDES resources •Identify the MMCM, PLL, and clock routing resources included with these families
  • Identify the hard resources available for implementing high performance DDR3 physical layer interfaces
  • Describe the additional dedicated hardware for all the 7 series family members
  • Properly code your HDL to get the most out of the 7 series FPGAs

Lab Description:

Lab 1: CLB Resources–Using XST, synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.

Lab 2: Memory Resources– Complete the RTL code required to infer a dual-ported block RAM. Explore the design using the RTL and technology viewers as well as the FPGA Editor. As an optional step, change the RTL code to infer a WRITE_FIRST block RAM.

Lab 3: DSP Resources– Using XST, synthesize and implement a 24×17 MAC. Device usage will be verified via the FPGA Editor. As an optional step, using the CORE Generator™ interface, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.

Lab 4: I/O Resources– Using the CORE Generator I/O Interface Wizard, construct a high-speed, clock-forwarded output interface. Explore through simulation the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the 7 series FPGA tile used for construction of the high-speed output interface

Lab 5: Clocking Resources– Using the Clocking Wizard, build and optimize the appropriate MMCM and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.

Course Outline:

1. 7 Series FPGA Overview

2. CLB Architecture

3. Slice Flip-Flops
Lab 1: CLB Resources

4. Memory Resources
Lab 2: Memory Resources

5. DSP Resources
Lab 3: DSP Resources

6. I/O Resources
Lab 4:
I/O Resources

7. Clocking Resources
Lab 5: Clocking Resources

8. Memory Controllers

9. Dedicated Hardware

10. Coding Techniques

Close Menu