Date 2,5/4/2020
Price 3,523 ILS + VAT /10 Tcs
DURATION 2 Days

Course Overview

Learn how to employ serial transceivers in your UltraScale™ FPGA design.
The focus is on:
  • Identifying and using the features of the serial transceiver blocks,such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection
  • Utilizing the UltraScale FPGAs Transceiver Wizard to instantiatetransceiver primitives
  • Synthesizing and implementing transceiver designs
  • Taking into account board design as it relates to the transceivers
  • Testing and debugging
  • This course combines lectures with practical hands-on labs.

Who should attend?

FPGA designers and logic designers

Prerequisite:

• Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
• Familiarity with logic design (state machines and synchronous design)
• Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
• Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools:

• Vivado® System Edition 2015.3
• Mentor Graphics Questa Advanced Simulator 10.4

Hardware:

• Architecture: UltraScale FPGAs*
• Demo board: None*

Skills Gained: After completing this training, you will be able to:

• Describe and utilize the ports and attributes of the serial transceiver in UltraScale FPGAs
• Effectively utilize the following features of the gigabit transceivers:
• 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
• Pre-emphasis and receive equalization
• Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
• Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
• Use the IBERT design to verify transceiver links on real hardware

Lab Description:

Lab 1: Transceiver Core Generation – Use the UltraScale FPGAs Transceivers Wizard to create instantiation templates.
Lab 2: Transceiver Simulation – Simulate the transceiver IP by using the IP example design.
Lab 3: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the UltraScale FPGAs Transceivers Wizard, simulate the design, and analyze the results.
Lab 4: Transceiver Implementation – Implement the transceiver IP by using the IP example design.
Lab 5: IBERT Design – Verify transceiver links on real hardware.

Course Outline:

1. UltraScale FPGA Overview
2. UltraScale FPGA Transceivers Overview
3. UltraScale FPGAs Transceivers Clocking and Resets
4. Transceiver Wizard Overview
5. Lab 1:
Transceiver Core Generation
6. Transceiver Simulation
7. Lab 2:
Transceiver Simulation
8. PCS Layer General Functionality
9. PCS Layer Encoding
10. Lab 3:
64B/66B Encoding
11. Transceiver Implementation
12. Lab 4:
Transceiver Implementation
13. PMA Layer Details
14. Transceiver Board Design Considerations
15. Transceiver Test and Debugging
16. Lab 5:
IBERT Design
17. Transceiver Application Examples

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