Start Date: 14/11/2023

Price 8,232 ILS
/ 24 Tcs


Course Overview

This comprehensive content is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. These courses address targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This training content combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization.



Who should attend?

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs


  • Basic digital design knowledge

Software Tools:

  • Vivado® Design Suite 2022.1


  • Architecture: N/A*
  • Demo board: Zynq® UltraScale+™ MPSoC ZCU104 board

Skills Gained: After completing this training, you will be able to:

After completing this training, you will be able to:

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a finite state machine (FSM) by using Verilog
  • Target and optimize AMD Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capabilities
  • Run a timing simulation by using AMD Xilinx Simprim libraries
  • Create and manage designs within the Vivado Design Suite environment
  • Download to the evaluation demo board

Lab Description:

Lab Description

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

Course Outline:

1. Hardware Modeling Overview
2. Verilog Language Concepts
3. Modules and Ports
4. Demo: Multiplexer
5. Lab 1: Building Hierarchy
6. Introduction to Testbenches
7. Lab 2: Verilog Simulation and RTL Verification
8. Verilog Operators and Expressions
9. Continuous Assign Statements
10. Lab 3: Memory
11. Verilog Procedural Statements
12. Lab 4: Clock Divider and Address Counter
13. Controlled Operation Statements
14. Lab 5: n-bit Binary Counter and RTL Verification
15. Verilog Tasks and Functions
16. Advanced Language Concepts
17. Finite State Machines
18. Lab 6: Finite State Machines
19. Targeting Xilinx FPGAs
21. Advanced Verilog Testbenches
22. Lab 7: Using Verilog File I/O