Start Date: 06/11/2023

Price 4,228 ILS
/ 12 Tcs


Course Overview

VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice. This training builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.

Who should attend?

Engineers, who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment.


Delegates attending only the Advanced VHDL module must have some hardware design experience, and have completed the VHDL for FPGA Design module or an equivalent course. We have found that delegates frequently overestimate their own capabilities.

Course materials

Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage are unique in the HDL training world and have made them sought after resources in their own right. Course fees include:

  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples to help you apply your knowledge

What will you learn?

The VHDL language concepts constructs essential for complex FPGA and ASIC design

  • The VHDL language constructs and coding styles that enable sophisticated test benches
  • How to code hierarchical designs using multiple VHDL design libraries
  • How to write re-usable, parameterisable VHDL code by exploiting generics and data types
  • How to run gate-level simulations


Course Outline:

1. More about Types

  • Variables
  • Loops
  • Std_logic and resolution
  • Array and integer subtypes
  • Aggregates

2. Managing Hierarchical Designs

  • Hierarchical design flow
  • Library name mapping
  • Component declaration
  • Configuration
  • Hierarchical configurations
  • Compilation order

3. Parameterised Design Entities

  • Array and type attributes
  • Port Maps
  • Generics and Generic Maps
  • Generate statement
  • Generics and generate


4. Procedural Testbenches

  • Subprograms
  • Procedures 
  • Functions
  • Parameters and Parameter Association
  • Package declarations
  • Package bodies
  • Subprograms in packages
  • Subprogram overloading
  • Operator overloading
  • Qualified expressions
  • RTL Procedures

5. Text-File-Based Testbenches

  • Assertions
  • Opening and closing files
  • Catching TEXTIO errors
  • Converting between VHDL types and strings
  • Checking simulation results
  • Initialising memories
  • Foreign bodies

6. Gate Level Simulation

  • Rationale for gate level simulation
  • VITAL tool flow
  • Reuse of RTL testbench at gate level
  • Comparison of RTL and gate level results
  • Behavioural modelling