This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado Design Suite. The features and capabilities of both the Zynq All Programmable System on a Chip (SoC), Zynq UltraScale+ MPSoC, and the MicroBlaze™ soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.
The Xilinx Zynq families enable a new level of system design capabilities over previous embedded technologies, which is highlighted throughout the course.
Level:Embedded Hardware 3
Who should attend?Engineers who are interested in developing embedded systems with the Xilinx Zynq® All Programmable SoC, Zynq UltraScale+™ MPSoC, and/or MicroBlaze™ soft processor core.
• FPGA design experience
• Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
• Basic understanding of C programming
• Basic understanding of microprocessors
• Some HDL modeling experience
• Vivado Design or System Edition 2017.3
Skills Gained: After completing this training, you will be able to:
• Describe the various tools that encompass a Xilinx embedded design
• Rapidly architect an embedded system containing a Cortex-A9/A53/R5 processor using the Vivado IP integrator and
• Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)
• Create and integrate an IP-based processing system component in the Vivado Design Suite
• Design and add a custom AXI interface-based peripheral to the embedded processing system
• Simulate a custom AXI interface-based peripheral using verification IP (VIP)
Driving the IP Integrator Tool
Describes how to access and effectively use the IPI tool.
Driving the SDK Tool
Introduces the basic behaviors required to drive the SDK tool to generate a debuggable C/C++ application.
Describes different types of AXI transactions.
Creating a New AXI IP with the Wizard
Explains how to use the Create and Import Wizard to create and package an AXI IP.
AXI: BFM Simulation Using Verification IP
Describes how to perform BFM simulation using the Verification IP.
MicroBlaze Processor Architecture Overview
Overview of the MicroBlaze microprocessor architecture.
Zynq-7000 All Programmable SoC Architecture Overview
Overview of the Zynq-7000 All Programmable SoC architecture.
Zynq UltraScale+ MPSoC Architecture Overview
Overview of the Zynq UltraScale+ MPSoC architecture.
1. Embedded UltraFast Design Methodology
Outlines the different elements that comprise the Embedded Design Methodology.
2. Overview of Embedded Hardware Development
Overview of the embedded hardware development flow.
3. Driving the IP Integrator Tool
Overview of Embedded Software Development
Reviews the process of building a user application.
4. Driving the SDK Tool
5. AXI: Introduction
Introduces the AXI protocol.
6. AXI: Variations
Describes the differences and similarities among the three primary AXI variations.
7. AXI: Transactions
8. Introduction to Interrupts
Introduces the concept of interrupts, basic terminology, and generic implementation.
9. Interrupts: Hardware Architecture and Support
Reviews the hardware that is typically available to help implement and manage interrupts.
10. AXI: Connecting AXI IP
Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
11. Creating a New AXI IP with the Wizard
12. AXI: BFM Simulation Using Verification IP
13. MicroBlaze Processor Architecture Overview
14. MicroBlaze Processor Block Memory Usage
Highlights how block RAM can be used with the MicroBlaze processor.
15. Zynq-7000 All Programmable SoC Architecture Overview
16. Zynq UltraScale+ MPSoC Architecture Overview