Price 1655 + VAT /5 Tcs
DURATION 1 Day

Course Overview

Learn how to use basic Tcl syntax and language structures to build scripts suitable for use with Xilinx FPGA design tools. Learn about the effective use of variables, data types, and Tcl constructs to build effective conditional statements and loop controls. You will also have the opportunity to use Tcl language constructs with several labs designed to provide you scripting experience within the Vivado™ Design Suite.

Level:

FPGA 1

Who should attend?

FPGA designers and logic designers

Prerequisite:

• FPGA design experience or completion of the Essentials of FPGA Design course

Software Tools:

• Vivado System Edition 2015.3

Hardware:

• Architecture: N/A*
• Demo board: None*

Skills Gained: After completing this training, you will be able to:

• Describe the basic syntax and language structure of the Tcl language
• Execute Tcl commands from a script using the Vivado IDE
• Use variables and describe data types
• Use Tcl language constructs to build conditional statements and loop controls for some common FPGA applications
• Use lists and arrays in efficient data structures
• Use procedures, packages, and namespaces to develop modules

Lab Description:

Lab 1: Introduction to the Vivado IDE Tcl Environment – Learn some basic ways of interfacing with the operating system and explore commonly used Tcl commands.

Lab 2: Xilinx Tcl Scripting – Learn how to use Tcl scripts in a typical FPGA design flow using the Vivado IDE.

Lab 3: Manipulating Pin Attributes with Tcl – Learn to query your design and verify the use of various Tcl commands with the Vivado IDE. You will also learn to make pin assignments and verify resource usage with appropriate Vivado IDE reports.

Lab 4: Design Analysis with the Vivado IDE – This lab introduces some of the most important reporting and design analysis features provided by the Vivado Design Suite. In this lab, you will use Tcl commands to query the design and locate clock sources. You will also use the check_timing and report_timing commands to verify design performance.

Lab 5: Using Regular Expressions – Query timing reports to find critical timing information and build a custom timing report while using file I/O commands and regular expressions to extract essential information with a script.

Course Outline:

1. Introduction to the Tcl Environment
2. Lab 1:
Introduction to the Vivado IDE Tcl Environment
3. Using Tcl in the Vivado IDE
4. Introduction to the Xilinx Tcl Store
5. Demo: Tcl Project-Based Flow
6. Introduction to the Xilinx Tcl Store
7. Demo: Using the Xilinx Tcl Store
8. Lab 2:
Xilinx Tcl Scripting
9. Basic Syntax and Structure
10. Data Types, Variables, and Expressions
11. Conditional Expressions and Loops
12. Lab 3:
Manipulating Pin Attributes with Tcl
13. Lists
14. Data Structures and Xilinx-Specific Tcl Commands
15. Lab 4:
Design Analysis with the Vivado IDE
16. Procedures and Packages
17. Tcl Regular Expressions
18. Lab 5:
Using Regular Expressions
19. Appendix: Debugging and Error Management
20. Appendix: Regular Tcl Expressions

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