Date 7-8.09.19
Price 3145 + VAT /10 Tcs
DURATION 2 Days

Course Overview

Verilog for VHDL Users is an intensive 2-day course, converting knowledge of VHDL to practical Verilog skills.
Contrasting Verilog and VHDL, this course demonstrates similarities and highlights differences between two hardware description languages and their associated design flows.
The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools.
Labs comprise about 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.
Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.

Who should attend?

Engineers proficient in VHDL who need migrate to Verilog or evaluate SystemVerilog

Prerequisite:

Delegates must have a good working knowledge of VHDL and digital hardware design

  • No previous knowledge of Verilog is required

 

Software Tools:

Standard Verilog 1364 complaint simulator

Course materials

Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage are unique in the HDL training world and have made them sought after resources in their own right. Course fees include:

  • Fully indexed course notes providing a concise Verilog reference
  • Workbook full of practical examples to help delegates apply their knowledge

What will you learn?

The differences and similarities between VHDL and Verilog

  • How to use the Verilog language for hardware design and logic synthesis
  • How to write thorough Verilog text fixtures to verify your designs
  • How to avoid common mistakes when coding Verilog for synthesis

 

Course Outline:

1. Introduction

  • What is Verilog?
  • Brief history and current status
  • The PLI
  • Scope of Verilog
  • Design flow
  • Verilog-2001
  • SystemVerilog
  • Verilog books and Internet resources

2. Differences between VHDL and Verilog

  • “Philosophy”
  • Red Tape
  • Strong typing
  • Determinisim
  • Data abstraction
  • Structure vs behaviour – Nets vs registers
  • Language structure – architecture, packages, configurations,files
  • Identifiers
  • Output ports
  • Implicit wires
  • Arrays
  • Aggregates
  • Signedness
  • Operators
  • Signal vs variables/nets
  • Process vs initial/always
  • If, case, loop differences
  • File i/o
  • Hierarchical names

3. Verilog Basics

  • Modules & ports
  • Continuous assignments
  • Comments
  • Names
  • Nets and strengths
  • Design hierarchy
  • Module instances
  • Primitive instances
  • Text fixtures
  • $monitor
  • Initial blocks
  • Logic values
  • Vectors
  • Registers
  • Numbers
  • Output formatting
  • Timescales
  • Always blocks
  • $stop and $finish
  • Using nets and variables correctly

4. Combinational Logic

  • Event control
  • If statements
  • Begin-endw Incomplete assignment and latches
  • Unknown and don’t care
  • Conditional operator
  • Tristates
  • Case, casez and casex statements
  • Full_case and parellel_case directives
  • For, repeat, while and forever loops
  • Integers
  • Self-disabling blocks
  • Combinational logic synthesis

 

5. Sequential Logic

  • Synthesising flip-flops & latches
  • Avoiding simulation race hazards
  • Nonblocking assignments
  • Asynchronous & synchronous resets
  • Clock enables
  • Synthesizable always templates
  • Designing state machines
  • State machine architectures
  • Verilog code-based FSM strategy
  • State encoding
  • Unreachable states & safe design practices
  • One-hot machines

6. Other features of Verilog

  • Verilog operators
  • Part selects
  • Concatenation & replication
  • Shift registers
  • Conditional compilation
  • Parameterisation and generate
  • Hierarchical names
  • Arithmetic operators and their synthesis
  • Signed and unsigned values
  • Memory arrays
  • RAM modelling and synthesis
  • $readmemb and $readmemh

7. Tasks and Functions

  • Understanding tasks
  • Task arguments
  • Task synchronization
  • Tasks and synthesis
  • Functions

8. Test Fixtures

  • File I/O – Writing to files; File access using MCDs; Reading  from files
  • Automated design verification using Verilog
  • Force and release
  • Gate-level simulation
  • Back annotation using SDF
  • “Traditional” Verilog libraries
  • Configuration and libraries
  • Command-line options
  • Behavioural modelling

9. Behavioural Verilog

  • Algorithmic coding
  • Synchronization using waits & event control
  • Concurrent-disabling of always blocks
  • Named events
  • Fork & join
  • High-level modelling using tasks, Implicit FSMs and  concurrent-disabling
  • Understanding intra-assignment controls
  • Overcoming clock skew
  • Blocking and nonblocking assignments
  • Continuous procedural assignment

10. Gate Level Verilog

  • Structural Verilog
  • Using built-in primitives
  • Net types & drive strengths
  • UDPs Gate, net & path delays
  • Specify blocks
  • Smart paths
  • Pulse rejection
  • Cell library modelling

11. SystemVerilog

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