Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools.
This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and 7 series FPGAs.
Who should attend?Engineers who seek advanced FPGA design training using Xilinx tools to improve FPGA performance and utilization while also increasing productivity.
Essentials of FPGA Design
- Designing for Performance
- Intermediate knowledge of Verilog or VHDL is strongly recommended
- At least six months of design experience with Xilinx tools and FPGAs
Xilinx ISE Design Suite: Logic or System Edition 14.7
- Architecture: 7 series FPGAs*
* This course focuses on the 7 seris FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
Skills Gained: After completing this training, you will be able to:
After completing this training, you will be able to:
- Create and edit a User Constraint File (UCF)
- Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfaces
- Implement designs via the Tcl command line
- Use the PlanAhead™ tool to create area constraints
- Use design preservation techniques to simplify design ripple effects
- Change signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor
Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.
Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.
Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.
Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.
Lab 6: FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.
2. Lab 1: Timing Closure Review
3. UCF Editing
4. Lab 2: UCF Editing
5. Advanced I/O Timing
6. Lab 3: Advanced I/O Timing
7. Tcl Scripting
8. Lab 4: Tcl Scripting
9. Floorplanning an Effective Layout
10. Lab 5: Floorplanning
11. Design Preservation Techniques
12. FPGA Editor: Viewing and Editing a Routed Design
13. Lab 6: Advanced FPGA Editor