Price 1655 + VAT /5 Tcs
DURATION 1 Day

Course Overview

This course describes the FPGA design best practices and skills to be successful using the Vivado™ Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an FPGA design methodology case study. The full FPGA Design Methodology Checklist is also introduced.

Level:

FPGA 3

Who should attend?

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.

Prerequisite:

• Some knowledge of FPGA design techniques is helpful
• Experience with the Vivado Design Suite or attendance of one of our existing Vivado Design Suite training courses is required
• Intermediate knowledge of Verilog or VHDL

Software Tools:

• Vivado Design or System Edition 2013.3

Hardware:

• Architecture: 7 series FPGAs**
• Demo board: None*

Skills Gained: After completing this training, you will be able to:

• Describe the Vivado Design Suite FPGA Design Methodology Checklist
• Identify key areas to optimize your design to meet your design goals and performance objectives
• Define a properly constrained design
• Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
• Build resets into your system for optimum reliability and design speed
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
• Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
• Identify timing closure techniques using the Vivado Design Suite
• Describe how the Xilinx design methodology techniques work effectively through case study/lab experience

Lab Description:

Lab 1: Resets – Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.

Lab 2: SRL and DSP Inference – Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for other common functions required by most FPGA designs.

Lab 3: Timing Closure and Design Conversion – Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted the dedicated hardware usage, design speed, and the device utilization.

Course Outline:

1. UltraFast Design Methodology Checklist

2. FPGA Design Methodology

3. HDL Coding Techniques

4. Reset Methodology
Lab 1: Resets
Lab 2: SRL and DSP Inference

5. Synchronization Circuits and the Clock Interaction Report

6. Timing Closure

7. FPGA Design Methodology Case Study
Lab 3: Timing Closure and Design Conversion

8. Course Summary

Appendix: Timing Constraints Review
Appendix: Synchronization Circuits and the Clock Interaction Report
Appendix: Fanout and Logic Replication
Appendix: Pipelining lab

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