Price 3145 + VAT /10 Tcs
DURATION 2 Days

Course Overview

FPGA Introduction assuming VHDL is a known language.

Level:

Fundamental.

Who should attend?

• Manager and project managers that have to better understand the projects they manage

Course Outline:

Day 1:
1. Basic FPGA Architecture
2. UltraScale Series FPGA Overview (Latest Greatest family)
3. Design Methodology
4. Introduction to Vivado
5. Lab1 – Vivado tool overview
6. Visualisation for Analysis
7. Design with IP in FPGA
8. Basic Timing constraint
9. Lab 2 – Vivado Synthesis and Implementation

Day 2:
10. Design with FPGA resources
11. Lab 3 – Design with FPGA resources
12. Debug with FPGA
13. Synchronisation design techniques
14. HDL coding technique
15. FPGA Configuration
16. Course summary

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