Price 3,523 + VAT / 10 Tcs

Course Overview

Over the years the use of communication networks has not only increased but also changed dramatically. Carriers today are aiming for a converged network that will supply data, audio and video communication on the same network infrastructure, providing a wide variety of new applications alongside the classical telephony, internet surfing, and TV broadcasting. To meet that goal the routers and switches in these networks and their underlying HW engines must improve. The HW engines are required to do diverse tasks from parsing and editing the packets, through forwarding them to scheduling them. Applying the right mechanisms for these diverse, demanding tasks requires an understanding in both networking and chip design. This course will discuss the context between the two fields with samples of Xilinx' implementations.

Who should attend?

ASIC/FPGA designers and system engineers implementing chips for networking applications.


Basic knowledge of a packet networking protocol (Ethernet, IP, MPLS…)

  • Experience in RTL design (VHDL or Verilog).



To become acquainted with existing HW solutions and understand their relation to the network requirements; to be able to choose the solution according to the requirements.

Course Outline:

1. Introduction

  • Current trends in networking
  • Where is dedicated HW solution required

2. Traffic Management

  • Basic components: queues, policers, schedulers
  • Efficient and scalable architecture for queuing
  • Two-rate-three-color metering policer
  • Basic schedulers: strict priority, round-robin, WRR, DRR
  • Concept of time and traffic shaping
  • Concept of virtual time and advanced scheduling (WFQ)
  • Xilinx' solution to Traffic Management

3. Switch Architectures

  • Basic architectures: shared memory, shared bus
  • Input queuing vs. output queuing
  • Advanced architectures: crossbar, banyan, clos
  • Inserting and extracting traffic: why we need it, where do we do it
  • A deeper look into multicasts

4. Example

  • Defining a switch architecture and TM schemes according to example network requirements


5. NPU – an inspiration for networking chips architecture

  • In-order processing
  • Out-of-order processing
  • Access to external engines

6. Packet Manipulations

  • Achieving flexibility at a reasonable cost
  • Xilinx core samples

7. Search and lookup engines

  • Requirements: fixed key length, longest prefix match, multiple keys
  • CAMas a basic building block
  • Implementing a small size CAM with logic
  • Advanced search engines – trees (optional)

8. High Availability (Optional)

  • In-service field upgrade with NPU
  • In-service field upgrade in FPGA
  • ECC – when do we need it
  • Simple implementation of ECC
  • Reliability in SRAM-based FPGA
  • Xilinx support of partial reconfiguration

9. Conclusion

  • Recap on course material
  • Stages for implementation
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