Start Date: 26/05/2024
Price 6,229 ILS
/ 18 Tcs
DURATION 3 Days
Course Overview
This course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool.
The focus of this course is on:
- Converting C/C++ designs into RTL implementations
- Learning the Vitis HLS tool flow
- Creating I/O interfaces for designs by using the Vitis HLS tool
- Applying different optimization techniques
- Improving throughput, area, latency, and logic by using different HLS pragmas/directives
- Exporting IP that can be used with the Vivado® IP catalog
- Downloading for in-circuit validation
Level:
DSP 3Who should attend?
Software and hardware engineers looking to utilize high-level synthesisPrerequisite:
- C or C++ knowledge
- Basic RTL design flow knowledge
Software Tools:
- Vitis HLS tool 2023.1
- Vivado Design Suite 2023.1
- Vitis unified software platform 2023.1
Hardware:
- Architecture: Zynq™ UltraScale+™ MPSoC and Versal™ AI Core series
- ▪ Demo board: Zynq UltraScale+ MPSoC ZCU104 board*
Skills Gained: After completing this training, you will be able to:
- Enhance productivity using the Vitis HLS tool
- Describe the high-level synthesis flow
- Use the Vitis HLS tool for a first project
- Identify the importance of the test bench
- Use directives to improve performance and area and select RTL interfaces
- Identify common coding pitfalls as well as methods for improving code for RTL/hardware
- Perform system-level integration of IP generated by the Vitis HLS tool
Lab Description:
- Vitis HLS Tool Flow
Explores the basics of high-level synthesis and the Vitis HLS tool. - Vitis HLS Tool Command Line Interface Describes the Vitis HLS tool flow in command prompt mode.
- Block-Level Protocols
Explains the different types of block-level protocols abstracted by the Vitis HLS tool. - Port-Level I/O Protocols
Describes the port-level interface protocols abstracted by the Vitis HLS tool from the C design. - Port-Level I/O Protocols: Memory Interfaces
Describes the memory interface port-level protocols (such as block RAM and FIFO) abstracted by the Vitis HLS tool from the C design. - Pipeline for Performance: PIPELINE Describes the PIPELINE directive for improving the throughput of a design.
- Pipeline for Performance: DATAFLOW Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible.
- Optimizing for Throughput Identify the performance limitations caused by arrays in your design. You will also explore optimization techniques to handle arrays for improving performance.
- Optimizing for Area and Logic
Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization. - HLS Design Flow – System Integration Describes the traditional RTL flow versus the Vitis HLS tool design flow.
- Vitis HLS Tool C++ Libraries: Arbitrary Precision
Describes Vitis HLS tool support for the C/C++ languages as well as arbitrary precision data types
Course Outline:
- Introduction to High-Level Synthesis
Overview of high-level synthesis (HLS), the Vitis HLS tool flow, and the verification advantage. - Vitis HLS Tool Flow
- Abstract Parallel Programming Model for HLS
Describes the structuring of a design at a high level using an abstract parallel programming model - Design Exploration with Directives
Explores different optimization techniques that can improve the design performance - Vitis HLS Tool Command Line Interface
- Introduction to Vitis HLS Design Methodology Introduces the methodology guidelines covered in this course and the HLS Design Methodology steps.
- Introduction to I/O Interfaces
Explains interfaces such as the block-level and port-level protocols abstracted by the Vitis HLS tool from the C design. - Block-Level Protocols
- Port-Level I/O Protocols
- AXI Adapter Interface Protocols
Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vitis HLS tool. - Port-Level I/O Protocols: Memory Interfaces
- Pipeline for Performance: PIPELINE
- Pipeline for Performance: DATAFLOW
- Optimizing for Throughput
- Optimizing for Latency: Default Behavior Describes the default behavior of the Vitis HLS tool on latency and throughput.
- Optimizing for Latency: Reducing Latency Describes how to optimize the C design to improve latency
- Optimizing for Area and Logic
- Migrating to the Vitis HLS Tool
Reviews key considerations when moving from the Vivado HLS tool to the Vitis HLS tool. - Vitis HLS Tool C++ Libraries: Arbitrary Precision
- Hardware Modeling
Describes hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class - Using Pointers in the Vitis HLS Tool
Explains the use of pointers in the design and workarounds for some of the limitations. {Lecture