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Price 4,228 ILS
DURATION 2 Days
Course Overview
This workshop is aimed at developers who want to implement high-speed interfaces between semiconductor components and who want to design complex high-speed circuits at board level. This Workshop is designed for developers who not only design schematics but also systems and the layout.
You will learn to judge when signal integrity is important and relevant, to interpret, for example, IBIS models, and to select appropriate termination procedures. Signal refection and crosstalk effects are described and demonstrated by simulation. Simulation examples are for typical PCB structures. You will learn how to implement high-speed buses, including clock design, loading and signal termination. Furthermore, the power distribution and bypassing design are main topics.
Detailed discussion of solving potential Signal Integrity problems on high-speed memory interfaces and serial transceiver links (optional modules).
Who should attend?
Hardware designers in generalPrerequisite:
• Basic knowledge on hardware design
Software Tools:
• Mentor Graphics HyperLynx 9.0
Skills Gained: After completing this training, you will be able to:
After completing this training, you will be able to:
• Understand circuit timing relationships
• Learn basics of IBIS simulation
• Understand reflection and crosstalk effects on PCBs
• Learn how to overcome reflection and crosstalk effects
• Apply for knowledge to more complex circuits
Course Outline:
1. Signal Integrity Basics
• Chip-to-Chip Timing
– Clocking schemes
– Setup and hold constraints, timing budget
– FPGA interface options
• IBIS Models for SI Simulation
– SI modeling, IBIS models, SI tools and usage of IBIS models
– LAB: Simulation example
• Transmission Lines
– Basics, critical trace length, designing transmission lines
– LAB: Transmission line parameters
2. SI Simulations
• Reflection
– Discussion reflection effect, reflection calculations, rules for solving reflection problems, reflection and circuit topologies
– LAB: Minimizing reflection
• Crosstalk
– Crosstalk effect, crosstalk calculations, rules for solving crosstalk problems
– LAB: Minimizing crosstalk
• SI-Analysis on System Level
– SI analysis methods, simulation elements, system analysis (example clock network, example high-speed parallel interface, example memory interface)
3. Implementing DDR3 Interfaces
• DDR3 Memory overview
• Controller design
– FPGA resources, design creation and parameter settings, example design
– LAB: DDR3 controller design
• Simulation and Implementation
– Simulation settings and functional verification, implementation settings and implementation, overview debugging options
– LAB: DDR3 controller simulation and implementation4. PCB-Level Design and Simulation of DDR3 Interfaces
• Memory interface design challenges
– Timing parameters and relationships, design requirements, examples
• Pre-layout analysis
– Methodology, simulation examples, parameter variation for timing optimization
– LAB: Timing analysis on selected nets
• Post-layout analysis
– Methodology – DDRx Wizard, collecting design parameters, preparing simulation, SI analysis, discussion of results
– LAB: Complete SI simulation DDR3 interface
• Design guidelines to overcome potential SI problems on memory interfaces5. Course Summary
• DDR3 Memory overview
• Controller design
– FPGA resources, design creation and parameter settings, example design
– LAB: DDR3 controller design
• Simulation and Implementation
– Simulation settings and functional verification, implementation settings and implementation, overview debugging options
– LAB: DDR3 controller simulation and implementation4. PCB-Level Design and Simulation of DDR3 Interfaces
• Memory interface design challenges
– Timing parameters and relationships, design requirements, examples
• Pre-layout analysis
– Methodology, simulation examples, parameter variation for timing optimization
– LAB: Timing analysis on selected nets
• Post-layout analysis
– Methodology – DDRx Wizard, collecting design parameters, preparing simulation, SI analysis, discussion of results
– LAB: Complete SI simulation DDR3 interface
• Design guidelines to overcome potential SI problems on memory interfaces5. Course Summary
