Price 6450 + VAT /16 Tcs
DURATION 4 Days

Course Overview

Course Description
Are you interested in learning how to effectively utilize 7 series high-speed interface resources? This course supports both experienced and less experienced FPGA designers who have in minimum general digital hardware knowledge and basic information on 7 series FPGAs. Furthermore, first work with the new Xilinx VIVADO Design Suite is helpful.  This course focuses on understanding as well as how to properly design for the high-speed interface solutions found in the new device families: transceiver in general, PCI Express and memory interfacing complemented with board design issues. Topics covered include interface overviews, design usage, simulation, implementation and examples on real hardware.
This course also includes a detailed discussion about proper PCB design techniques that enables designers to avoid common mistakes and get the most out of their FPGA interfaces.
A combination of modules and labs allow for practical hands-on application of the principles taught.

Who should attend?

• Xilinx hardware designers

Prerequisite:

• Essentials of FPGA Design course
• Intermediate VHDL or Verilog knowledge

Software Tools:

• VIVADO Design Suite 2012.3

Hardware:

• 7 Series FPGAs and ZYNQ-7000
• Demo board: KC705

Skills Gained: After completing this training, you will be able to:

• Describe the functionality of transceivers, PCIe blocks and memory interfaces
• Configure the corresponding wizards to design high-speed interfaces
• Simulate and implement high-speed interfaces
• Start practical work with high-speed interfaces
• Describe challenges and solutions for successful powering and interfacing high-speed interfaces on PCB level
• Apply high-speed interface specific  signal integrity rules in PCB design

Course Outline:

1. Introduction to high-speed connectivity

2. Serial transceiver

3. Transceiver overview (7 series FPGAs and Zynq 7000)

4. Basic principles and solutions in serial transmission

5. Transceiver design
Lab 1: Generating transceiver design (GTX)

6. Simulation transceiver interfaces
Lab 2: Transceiver simulation (GTX)

7. Implementing transceiver interfaces
Lab 3: Transceiver implementation (GTX)

8. Debugging transceiver interfaces
Lab 4: IBERT (GTX)

9. PCI Express

10. PCIe Basics

11. Xilinx PCIe solutions

12. PCIe endpoint design
Lab 5: Generating PCIe endpoint

13. Simulation PCIe interfaces
Lab 6: PCIe endpoint simulation

14. Implementing PCIe interfaces
Lab 7: PCIe endpoint implementation

15. Usage of PCIe endpoint in application
Lab 8: PCIe endpoint in real system with KC-705 board

16. Memory Interfaces

17. Memory devices overview

18. Xilinx memory interface solutions

19. DDR3 design
Lab 9: Generating DDR3 controller

20. Simulation memory interfaces
Lab 10: DDR3 interface simulation

21. Implementing memory interfaces
Lab 11: DDR3 implementation

22. Usage of memory interface in application
Lab 12: Verification DDR3 interface on real hardware (SODIMM DDR3 1600 Mbps)

23. 7 Series / Zynq Board Design

24. General design constraints

25. Signal integrity on chip level (IO region)

26. Power options, requirements and solutions

27. Power estimation in XPE vs. Power calculations in Vivado

28. Powering transceivers – requirements and solutions

29. Powering memory interfaces – requirements and solutions

30. Board design for Agile Mixed Signal

31. Signal integrity on board level

32. Board design checklis

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