Price 3095 + VAT /10 Tcs
DURATION 2 Days

Course Overview

Learn when and how to apply signal integrity techniques to high-speed interfaces between FPGAs and/or other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed routing and clock design, including transmission line termination, loading, and jitter. You will gain the understanding of Multi-Gigabit serial Transceivers TX & RX architectures and operation though a deep dive in to Xilinx GTH & GTY High-speed Serial Transceivers.
You will work with S-parameters, IBIS & IBIS-AMI models and complete Pre-layout and Post-layout simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects, on-chip termination and TX/RX equalization.
This course balances lecture modules with instructor demonstrations and practical hands-on labs.

Level:

Connectivity 3

Who should attend?

Digital designers, High speed designers, board layout designers, or scientists, engineers, and technologists seeking to implement Multi-Gigabit High speed links. Also end users of Serial transceivers who want to understand how to implement Gigabit high-speed interfaces without incurring the signal integrity problems related to timing, reflection, crosstalk, Inter-symbol interference and overshoot or undershoot infractions.

Prerequisite:

.• FPGA board design experience preferred (Essentials of FPGA Design course or equivalent)
• Familiarity with high-speed PCB concepts
• Basic knowledge of digital and analog circuit design
• Mentor Graphics HyperLynx ® tool knowledge is helpful

Software Tools:

• Mentor Graphics HyperLynx VX.2.3

Skills Gained: After completing this training, you will be able to:

• Describe signal integrity effects, Predict and overcome signal integrity challenges
• Simulate signal integrity effects using IBIS- & IBIS-AMI models at High Multi-Gigabit rates
• Learn the theory and simulate Single-ended and Multi-mode S-parameters high frequency design techniques
• Understand high frequency PCB design techniques design flows including Hands-on tips
• Understand Serial transceivers usage with both TX & RX equalization signal impairments including Hands-on tips
• Design Multi-Gigabit high speed links through high frequency design flow: S-parameters, Pre-Layout and Post-Layout simulations
• Debug high speed Multi-Gigabit links via High frequency techniques such as multi-mode S-parameters
• Apply signal integrity techniques to high-speed interfaces between FPGAs other semiconductor circuits
• Plan your board design under FPGA-specific restrictions
• Supply the FPGAs with proper power & Reference Clock
• Understand Multi-Gigabit High speed links through Analog/RF point of view and not just from plain Digital perspective

Lab Description:

Lab 1: Pre-layout signal integrity
Become familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stack-up editor to define
a PCB. Define a circuit and run various simulations for effects of reflection.

  Lab 2: S-parameters lab
• Introduction to S-parameters Theory
• High frequency transmission lines Insertion loss return loss
and isolation modeling
• High frequency SMT pads and Vias discontinuities modeling

Lab 3: Pre-layout simulation with IBIS AMI (~25Gbps)
Lab includes a Simulation of 2 use-cases:
• Use case 1: Getting to know IBIS AMI capabilities – On board
FPGA to FPGA GTY transceivers link analysis
• Use case 2: Design of a mid-plane board to connect 2 Xilinx
FPGA EVBs GTY transceivers link

Lab 4: Post-layout simulation with IBIS AMI (~25Gbps)
• Post-layout simulation with IBIS AMI simulating “use case 2”
of previous lab, including a Full board layout file upload to
Hyperlynx Simulator

Course Outline:

Part 1 – Signal Integrity

1. Signal Integrity Introduction
• What is High Speed Board Design
• Digital Vs. Analog world
• Various effects on electrical signal
• Describe the nature of a transmission line
• Explain the significance of harmonic magnitude
• Discuss the importance of rise and fall times
• Identify general issues relating to signal integrity design

2. Transmission Lines
• Theory Basic transmission line
• Critical Trace Length in the Time Domain
• Critical Trace Length in the Frequency Domain
• Propagation Delay Time on Layers: External & Internal
• PCB Conductors
• Distributed T-Line Representation
• Low Frequency versus High Frequency Return Path
• Lossy Lines vs. Lossless Lines
• Skin Effect, Skin depth calculation

3. Reflections
• Describe the effect of reflection
• Reduce the reflection by termination
• Describe the reflection for different topologies
• Simulate reflection effects

4. Crosstalk
• Simulate reflection effects on a baseline circuit
• Reduce reflection effects by using various terminations: serial, pull-up, pull-down, and Thevenin resistors
• Crosstalk Calculations
• Minimizing Crosstalk

5. Case Study – Short exercise on Via, correct termination,  
impedance matching and troubleshooting

Lab 1: Pre-layout signal integrity

6. Signal Integrity Summary

Part 2 – Board Design & High-speed Serial Transceivers

7. Transceiver Overview
• Motivation for Serial I/O
• Architectures and Protocols
• Ultra-Scale FPGA GT Solution
• GT Tile
• GT Transmitter
• GT Receiver
• Ease of Use

  Lab 2: S-parameters lab

8. Physical Media Attachment Layer
• Overview
• TX Polarity Control and PISO
• TX Driver & pre-emphasis equalization
• RX Termination and Equalization
• RX CDR
• RX Margin analysis
• Eye scan architecture
• RX SIPO and Polarity Control

Lab 3: Pre-layout simulation with IBIS AMI (~25Gbps)

9. Board design consideration for serial transceivers
• Transceiver Board Interface
• Power filtering
• Resistors calibration
• Transceiver Board Design & Layout guideline
• Reference CLK guidance
• Transceiver Signal Integrity including IBIS-AMI models
• S-parameters modeling (Via Stub, SMT pads, Microstrip / Stripline bends)

Lab 4: Post-layout simulation with IBIS AMI (~25Gbps)

  10. Board Design & High Speed-Serial Transceivers
Summary

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